SPARC64™ V Background Briefing

Design Goals

• Solaris™ Operating System and its applications
  
• Versatility
  
• High Performance
  
• Mainframe level RAS (Reliability, Availability and Serviceability)
  

We set four major design goals for our SPARC64™ V development.First, SPARC64™ V must be SPARC V9 compliant and hardware compatible for Solaris. This ensures we can run the latest Solaris versions and all applications.

Second, SPARC64™ V must be versatile, and suitable for use in a range of systems. This included Low power consumption, Simplified mounting and a relatively small number of signal pins to ensure cost effectiveness, System high reliability and easy field upgrading and exchange. This also enabled us to use the exact same SPARC64™ V processors in small front-end servers and the largest HPC SMP servers in the world.

Third, SPARC64™ V must achieve performance. SPARC64™ V is achieving high performance in both enterprise computing environments like LTP ERP ,and in the R&D/HPC area.

Forth, SPARC64™ V should introduces mainframe class RAS to respond to the mission critical UNIX server market.

SPARC Technology

- GHz Processor, adopts advanced micro-architecture -

• 1.35/1.89/2.16GHz Frequency
  90nm CMOS Copper Technology
• Parallel & out-of-order execution
  -6 arithmetic units
  -4 floating-point operations
  -Non-blocking cache
• Large on-Chip low latency L2 Cache
  
• 16 outstanding memory access and high throughput buses
  

SPARC64™ V is fabricated using 90nm CMOS technology with copper metalization, and it operates at Max1.89GHz. The internal microarchitectue of SPARC64™ V is a super-scalar with out-of-order execution mechanizm. High throughput is major objects of microarchitecture of SPARC64™ V.

It has two integer units, two floating-point units and two address generation units, that is, totally 6 arithmetic units. Both floating-point units can execute multiply & add, then you may count up four floating-point operations executed at the same time. SPARC64™ V has two level non-blocking cache on the same die. Level 1 caches are 128KB for instruction and 128KB for data. Level 2 cache is Max 4MB. They are connected low latency high-throughput bus.

Memory access throughput is also important factor of the performance. So, SPARC64™ V can issue up to sixteen memory requests at once, and interface bus clock can operate at 270MHz. With these high-throughput design, SPARC64 ™ V will draw out system's potentiality, and maximize the performance of PRIMEPOWER.