Memory Interleave for Increased Memory Access Efficiency
PRIMEPOWER supports memory interleave, which boosts memory access performance via parallel access to multiple on-board memory units. This is especially beneficial for HPC applications such as scientific calculations involving large volumes of data.
In cases where high-volume data must be read consecutively from memory, memory access wait times can become performance bottlenecks. This feature permits large data volumes to be read from multiple memory areas successively to reduce the processing timeassociated with memory access.
PRIMEPOWER 650 for example is capable of accessing four memory chips successively in parallel. In memory interleave mode, up to 32 memory chips can be accessed successively in parallel.
This feature is found in PRIMEPOWER 650 and larger systems.
Technical description: Mechanism of memory interleave
PRIMEPOWER uses SDRAM(*). For SDRAMs, row and column addresses are specified with times similar to that shown in Fig. 2, and data is read separately in two blocks.
The access paths from the memory controller to memory are limited; only one set of paths is available for address and data, respectively. Reading large data volumes from one memory chip can be time-consuming. For this reason, the internal memory architecture is configured in four layers (banks) to increase data read performance.
Memory interleaving in PRIMEPOWER further expands this concept to achieve parallel accesses to multiple memory chips.
This feature is highly effective for reading large volumes of data in succession. This is particularly helpful with HPC applications involving high-volume computing operations. The benefits are less dramatic for processing that involves reading randomly located data.
(*) SDRAM refers to Synchronous DRAM, a memory standard.
