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Advanced Silicon Device Technologies

FSTJ 2003-6 Cover Image

2003-06 (Vol.39, No.1)

This special issue on Advanced Silicon Device Technologies describes the results of recent research on the performance and reliability of the next and future generations of CMOS devices, key process technologies, and simulation technologies that support further development of CMOS.

2003-06 (Vol.39, No.1) Contents

1. Preface (27 KB)
We hope that this special issue will help readers grasp the various technical aspects of Silicon Device Technologies and use our CMOS devices to find and develop new technology application areas. ---[Tetsuo Nakamura, Senior Vice President, Fujitsu Laboratories Ltd. ]

CMOS device performance and reliability improvements

2. Research and Development of Advanced CMOS Technologies (73 KB)
Advanced CMOS technologies will be very important keys for increasing system performance in the coming information society. To meet market requirements, Fujitsu is continuously making developments in leading-edge CMOS technologies and supplying them to captive systems as well as to outside consumers. This paper describes the current status of Fujitsu's R&D for next-generation CMOS and beyond. --- [Takashi Ito]
3. Transistor Design for 90 nm-Generation and Beyond (220 KB)
In this paper, we review recent trends in MOSFET scaling such as the aggressive scaling of gate length, the decrease in on-current with scaling, and the increased demand for a variety of transistor types for use in a wide range of target products. To keep up with these trends, there are many device and process issues that need to be resolved. We have categorized these issues and developed new technologies for 90 nm-node transistors. We have fabricated a 90 nm-node transistor with a high on-current and a 40 nm gate length, which is the shortest gate length reported so far for 90 nm transistors. To continue performance improvement for the 65 nm node, it will be necessary to introduce new materials such as high-k gate insulators and breakthrough technologies such as laser annealing. In this paper, we also describe the potentials of these new technologies. --- [Toshihiro Sugii, Kiyoshi Watanabe, Shinji Sugatani ]
4. Integration of High-Performance Transistors, High-Density SRAMs, and 10-level Copper Interconnects into a 90 nm CMOS Technology (285 KB)
This paper presents a 40 nm-gate-length transistor, an ultra-high-density 6T SRAM cell, 10-level Cu interconnects, and very-low-k (VLK) dielectrics for high-performance microprocessor applications. The key process features are 1) 193 nm lithography with a phase shift mask (PSM) and optical proximity correction (OPC) that enables us to fabricate a 40 nm-long gate and a sub-1 µm² SRAM cell, 2) a unique transistor feature called a sidewall-notched gate that enables optimal pocket implant placement and suppresses variations of the notch width much better than a poly-notched gate structure, 3) a 1.1 nm-thick nitrided oxide to achieve a high drive current and a reduced thermal budget to suppress boron penetration, and 4) an SiC-capped Cu/SiLKTM structure in 0.28 µm-pitch Metal 1-4 layers that realizes a keff of 3.0. --- [Satoshi Nakai, Tsutomu Hosoda, Yoshihiro Takao]
5. Extended 90 nm CMOS Technology with High Manufacturability for High-Performance, Low-Power, RF/Analog Applications (154 KB)
High-density, 90 nm CMOS technology has been suggested for generic, low-voltage, high-performance applications. In this paper, we describe some strategies for extending the previous technology in order to fabricate the following: 1) a low-standby-power transistor with high drivability for low-power applications, 2) a high-drivability transistor, inductor, and MIM capacitor for RF/analog applications, 3) up to 10 layers of high-reliability, dual damascene Cu/very-low-k (VLK) and Al interconnects. Our low-standby-power, 90 nm transistor consumes only 10% of the standby power consumed by 130 nm transistors, and this is achieved with no degradation of circuit speed. Using 90 nm technology, we have fabricated up to 10 layers of interconnects and a 1.07 µm² SRAM cell without additional process steps such as local interconnects and shared contacts. We have also used this technology to manufacture a fully-functional SRAM macro and increased its yield by improving the hard mask process for Cu/VLK interconnects and optimizing the gate polypattern. Also, a full, low-k (FLK) interlayer dielectric (SiLK) structure shows superior performance and reliability compared to similar 130 nm structures. --- [Yoshihiro Takao, Satoshi Nakai, Naoto Horiguchi ]
6. Impact of Nitrogen Profile in Gate Nitrided-Oxide on Deep-Submicron CMOS Performance and Reliability (256 KB)
Silicon dioxide has been used for the gate insulator in CMOS with gate lengths down to 0.25 µm. However, when we enter the sub-0.18 µm era, nitrogen atoms must be incorporated into the silicon dioxide to prevent an undesirable penetration of boron atoms from the gate electrode to the Si substrate. In this paper, we describe the effects of the nitrogen atom profile on CMOS performance and reliability and clarify the mechanisms underlying these effects. We show that high-performance, high-reliability CMOSFETs can be achieved by using a newly developed nitrided-oxide process that features a 900°C gate nitrided-oxide and establishes different nitrogen concentrations between the gate and extension area. When we enter the sub-100 nm-gate-length era of CMOS, we will need to replace thermal nitridation for the gate oxide with an alternative nitridation process, for example, plasma nitridation. --- [Kanetake Takasaki, Kiyoshi Irino, Takayuki Aoyama, Youichi Momiyama, Toshiro Nakanishi, Yasuyuki Tamura, Takashi Ito ]
7. A Secure Dynamically Programmable Gate Array Based on Ferroelectric Memory (271 KB)
The field programmable gate array (FPGA) market is expanding because FPGAs enable faster development times and lower development costs than mask programmable gate arrays (MPGAs). However, the conventional SRAM-based FPGA requires off-chip, non-volatile PROMs to store configuration data, which increases the total device cost and the board area. To provide a low-cost solution for field programmable devices, we have developed a non-volatile, 8-context, dynamically programmable gate array (DPGA) using ferroelectric RAM (FeRAM) technology. The developed configuration memory, which consists of a SRAM-based 6-transistor/4-ferroelectric-capacitor cell, has an access time comparable to that of a standard SRAM. It also has a non-destructive read operation and a stable data recall scheme. In addition, the contents of the configuration memory are securely protected. We have fabricated a prototype DPGA that combines 0.35 µm CMOS and FeRAM technologies. Using this device, we have executed the Data Encryption Standard (DES) functions at up to 51 MHz at 3.3 V. We confirmed that the minimum non-volatile operating voltage is 1.5 V. --- [Michiya Oura, Shoichi Masui]
8. Process and Device Technologies for High-Performance 0.13 µm FCRAM (179 KB)
We have developed a novel integration scheme for FCRAM cores using a high-dielectric capacitor technology and low-temperature process technology so we can scale the design rule towards 0.13 µm and improve device performance. Ru/Ta2O5/Ru capacitor technology, which can provide a dielectric constant as high as 70 and an SiO₂-equivalent thickness of 0.7 nm, has been established combined with a robust cylinder electrode fabrication process using a TiN liner. A self-aligned storage-node contact fabrication process with low-temperature (600°C) Si₃N₄deposition improves the transistor performance by more than 10%. These technologies have been applied to a 0.13 µm-generation device, and the functionality of this device has been confirmed. Also, this paper demonstrates the scalability of these technologies to the 0.1 µm generation. --- [Yasuo Nara, Shunji Nakamura, Tetsu Tanaka, Koichi Hashimoto, Daisuke Matsunaga]
9. Direct Tunneling Memory (97 KB)
To realize a random accessible storage device, we propose the Direct Tunneling Memory (DTM). This is a sub-0.1 µm floating gate memory that uses direct tunneling at a lower operating voltage than flash EEPROM: the applied word line voltage of DTM is 6 V, and the bit line voltage is 2 V. The oxide barrier of DTM memory is 3 nm or less, which is much thinner than the 10 nm oxide barrier of flash EEPROM (10 nm). However, the new structure has a long retention time. The DTM structure can be made using a logic compatible fabrication-process, since, unlike FeRAM and MRAM, it does not use any new materials. We will use DTM to fabricate a large, low power consumption memory that can be embedded into a System-on-a-Chip (SOC). --- [Tatsuya Usuki, Kouji Tsunoda, Akira Sato, Toshiro Nakanishi, Hitoshi Tanaka]
10. <100> Strained-SiGe-Channel p-MOSFET with Enhanced Hole Mobility and Lower Parasitic Resistance (63 KB)
Employment of the <100> channel direction in a strained-Si0.8Ge0.2 p-MOSFET provides a hole mobility enhancement as large as 25% and a parasitic resistance reduction of 20% compared to a <110> strained-Si0.8Ge0.2 channel p-MOSFET, which already has a better mobility and threshold voltage roll-off than the Si p-MOSFET. These results suggest that the <100> strained-SiGe-channel p-MOSFET can be used to achieve high-speed CMOS devices that operate at low voltages. --- [Masashi Shima]

Process technologies

11. Reliability Improvement in Deep-Submicron nMOSFETs by Deuterium (389 KB)
This paper reviews recent experimental and theoretical findings critical for process integration of deuterium post-metal anneals to improve hot-electron reliability in deep-submicron Si CMOS circuits. After the first demonstration using deuterium, this concept has been reproduced and extended by several other researchers. In this paper, we propose a mechanism that explains the large improvement in hot-electron reliability that is observed when deuterium is introduced. We also describe spectroscopic experiments we made that support this mechanism, including its treatment of the dissipation of excited vibrational energy to the substrate silicon lattice. --- [Satoru Watanabe, Yasuyuki Tamura]
12. Approaches to Using Al₂O₃ and HfO₂ as Gate Dielectrics for CMOSFETs (137 KB)
We report on recent approaches to using Al₂O₃ and HfO₂ in MOSFETs. A MOS diode with an Al₂O₃ gate dielectric into which dimethylhydrasin (DMH) was doped shows a minimum Dit of 4 × 10¹º cm-2eV-1, which is half that of Al₂O₃. Mobility enhancement and an increase of saturation current were obtained with the DMH-doping. A SiN/HfO₂/SiON gate stack was found to suppress HfO₂/polysilicon reaction and dopant diffusion. The base oxide of SiON also helps to improve the reliability and thermal stability of the gate stack. An inversion EOT of 1.7 nm was obtained with a SiN/HfO₂/SiON gate stack that shows a saturation current of 357 µA/µm at Lg of 0.35 µm. A 55 nm CMOS with a 3 nm HfO₂gate dielectric was fabricated using high-temperature annealing at ≥ 1000°C and cobalt silicide. Gate leakage current was decreased by more than three orders of magnitude and a low off-state current was obtained. We also investigated the thermal stability of HfxAl1-xOy. Within 0 ≤ x ≤ 0.8, HfxAl1-xOy stays amorphous up to 800°C, which is 300°C higher than the corresponding temperature for HfO₂. --- [Yoshihiro Sugiyama, Sergey Pidin, Yusuke Morisaki]

Advanced simulation technologies

13. Nano-Scale Simulation for Advanced Gate Dielectrics (368 KB)
As a result of aggressive scaling of CMOS (Complementary Metal-Oxide-Semiconductor) transistors, the thickness of the gate insulator is approaching atomic dimensions. In advanced CMOS with such ultrathin dielectric films, atomic-scale phenomena play an important role in performance and reliability. Simulation is a powerful tool for investigating and understanding atomic scale phenomena. We investigated the electronic properties of the Si(100)/SiO₂ interface with the first-principles molecular dynamics method. The behavior and the electronic properties of the defect, hydrogen, and nitrogen atoms at the interface, which have a serious influence on the electronic properties of the insulating film, were also investigated. We also simulated the annealing behavior of aluminates and silicates of Hf and Zr, which are candidates for the high-dielectric-constant gate dielectric materials of future CMOS, by employing the classical molecular dynamics method. From the results of our simulation, we can obtain a guideline to control the gate dielectric materials and the interfaces with the Si substrate. --- [Chioko Kaneta, Takahiro Yamasaki, Yuko Kosaka]
14. Equivalent Circuit Model of ESD Protection Devices (81 KB)
In this paper, we propose an equivalent circuit model that describes the snapback characteristics of ESD (ElectroStatic Discharge) protection devices constructed using MOS transistors. Our goal was to predict the ESD immunity of CMOS integrated circuits using circuit simulations. The ESD immunity can be predicted from the high-current behavior (the snapback characteristics) of the protection devices. In this paper, we explain our equivalent circuit model, which includes a parasitic bipolar transistor with a generated-hole-dependent base resistance. Because the models for parasitic elements are combined with a SPICE MOS transistor model, our model can represent the gate bias dependence of snapback characteristics. The equivalent circuit parameters are extracted from the device simulations and modified to reproduce the measured snapback characteristics of the MOS transistor. Therefore, our equivalent circuit model for MOS protection devices can be used in ESD circuit simulations.--- [Hiromi Anzai, Yoshiharu Tosaka, Kunihiro Suzuki, Toshio Nomura, Shigeo Satoh]
15. Atomistic Simulation for Shallow Junction Formation (259 KB)
IThis paper presents an atomistic model for ion implantation and annealing to simulate shallow junction formation. In our code, the newest physical models are included and a great number of efficient algorithms are used to conduct realistic and accurate simulations. By comparing our simulation results with SIMS data for B and As ranging from 0.5 keV to more than 100 keV implantation, we verified the correctness and efficiency of our code. The annealing simulation is carried out for RTA (Rapid Thermal Annealing) at 1000°C or 1050°C after B implantation. The implantation energy was varied from 0.5 to 5 keV. Agreements between the simulations and SIMS data were achieved, and the simulations accurately characterized both BED and TED phenomena. --- [Hideki Oka, Kunihiro Suzuki, Zhang Jinyu, Min Yu, Ru Huang]
16. Model for Transient Enhanced Diffusion of Ion-Implanted Boron, Arsenic, and Phosphorous over Wide Range of Process Conditions (322 KB)
We obtained experimental transient enhanced diffusion profiles of boron, arsenic, and phosphorous over a wide range of process conditions. We analyzed these data using a one-dimensional process simulator. By using a simple, empirical methodology for initial super-saturated interstitial Si profiles and a dynamic impurity clustering model, we succeeded in reproducing transient enhanced diffusion profiles with a single parameter set. --- [Kunihiro Suzuki]
17. A New Method for Monitoring Electron Temperature in Si Plasma Etching (57 KB)
This paper proposes a new method for monitoring the electron temperature in silicon plasma etching. The method is based on the maximum charging voltage that can be established by a local charge build-up at the bottom of a capillary having a high aspect ratio. The method is demonstrated for inductively coupled plasma (ICP) in argon by using a quartz chip containing an array of 400 µm-long, 20 µm-diameter capillaries. The maximum charging voltage is linearly related to the electron temperature. The charging voltage, however, is lower than the theoretical sheath voltage by 4.3 V over electron temperatures from 2.2 to 4.0 eV. From numerical simulations, this voltage difference is due to the potential barrier against ion movement in the capillary. Therefore, the voltage difference is independent of the electron temperature and this method can be used for relative measurement of electron temperature. --- [Takeshi Goto]

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