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System-on-a-Chip (SOC)


FSTJ 2000-06 Cover Image

2000-06(Vol.36, No.1)



2000-6 (Vol.36, No.1) Contents

1. Preface (62 KB)
---[Tetsuo Nakamura , Member of the Board Fujitsu Laboratories Ltd . ]

Design Methodologies

2. IPHighway:Infrastructure for IP Macro Distribution (267 KB)
Recent sub-micron technology has made it possible to realize system LSIs which integrate various system functions. However, system-level integration brings enormous difficulties to LSI designers. It has been pointed out that the reuse of IP macros is a very effective way to overcome these difficulties. This paper describes the issues that are necessitating the reuse of IP macros and our IPHighway system, which we have constructed internally for promoting the reuse of IP macros. Also, recent activities in the industry for distributing IP macros between companies are described. ---[Akinori Tahara, Minoru Yamamoto, Muneo Hokosaki ]
3. Techniques for Effectively Applying Model Checking to Design Projects (136 KB)
This paper describes some techniques for applying model checking to actual design projects. Because of the rapid growth of digital systems, logic verification will be a main problem in the design flow. Although simulation-based verification has been adopted, it is widely accepted that the evolutionary progress of simulation techniques will not provide a solution to the verification crisis. We have been conducting research on formal verification, especially on model checking. We have developed some advanced techniques that should work effectively on actual designs and have applied our tool "BINGO" to some design projects. This paper compares model checking with simulation-based verification. It also describes how to use model checking techniques complementally with simulation. ---[Tsuneo Nakata, Satoshi Kowatari, Hiroaki Iwashita, Koichiro Takayama ]
4. An Efficient Filter-based Approach for Combinational Verification (119 KB)
We have developed a filter-based framework where several fundamentally different techniques can be combined to provide fully automated and efficient heuristic solutions to verification and possibly other NP-complete problems. Such an integrated methodology has been shown to be far more robust and efficient than any single existing technique on a wide variety of circuits. ---[Jawahar Jain, Rajarshi Mukherjee, Koichiro Takayama]
5. Verification Methodology for a Complex System-on-a-Chip (228 KB)
Semiconductor technology has progressed to the point where it is now possible to implement system-level functions on a single LSI chip. However, traditional LSI verification becomes less and less powerful as the scale and complexity increase. In fact, more than half of the time required to develop a System-on-a-Chip (SOC) is used for function verification. A new verification methodology for SOCs should therefore be established. We developed a system-level simulation technology to verify the specification and architecture of an SOC and a logic emulation technology to verify the logic function of an entire SOC. By combining these technologies, we established a powerful verification methodology for an SOC. We applied the verification methodology to develop a high-definition MPEG2 decoder LSI for a digital TV broadcasting system. The LSI was successfully developed on schedule and worked in the first silicon implementation completely according to the specifications. ---[Akihiro Higashi, Kazuhide Tamaki, Takayuki Sasaki ]

Processors

6.FR500 VLIW-architecture High-performance Embedded Microprocessor (316 KB)
A new-concept FR500 microprocessor using the VLIW architecture has been developed for digital consumer products. It can issue four instructions simultaneously and can be configured in a small-scale circuit, making it possible to implement a low-cost, high-performance system. It combines two 32-bit integer operation units, two 32-bit floating-point operation units, and two 16-bit media processing operation units, providing a peak performance of 532 MIPS, 1064 MFLOPS, and 4256 MOPS at 266 MHz. The flexible instruction set provided by the VLIW architecture makes it possible to add specialized DSP instructions for signal processing as well as customer-defined instructions. This enables development of a microprocessor optimized for digital consumer products - a market that is expecting explosive growth. ---[Takao Sukemura]
7. Four-way VLIW Geometry Processor for 3D Graphics Applications (300 KB)
A four-way Very Long Instruction Word (VLIW) geometry processor that can be applied to PC-based CAD systems has been developed. PC-based CAD systems require a very high graphics performance and a very high cost effectiveness. To achieve a high performance, Single Instruction Multiple Data Stream (SIMD) instructions specialized for geometry operations were implemented and a unique architecture called the "software bypass mechanism" was adopted. To reduce system cost, PCI and AGP interface logics were implemented within the processor, so the processor can be applied to PC-based systems without using bus interfacing LSIs. The processor can issue up to four instructions at a time based on a four-way VLIW architecture. A performance of 2.5 GFLOPS and 6.5 Mp/s (mega polygons per second) was achieved at an operating frequency of 312 MHz. The processor was fabricated with a 0.21 µm CMOS process technology on a 9.18 mm x 9.11 mm die. ---[Hajime Kubosawa, Naoshi Higaki, Hiromasa Takahashi ]
8. Single-chip MPEG2 MP@HL Decoder with Multi-decode and Seamless Display Features (466 KB)
This paper reports on the development of an MPEG video decoder LSI. The new LSI can process MPEG MP@HL, which contains six times as much information as the normal MPEG MP@ML used in DVDs and CS digital broadcasting, and can receive HDTV broadcasts. Also, the chip has a multi-decode and seamless display capability for use in the digital broadcasts of the future. This paper gives an outline of the new chip and its architecture and describes the realization of the multi-decode and seamless display functions. ---[Hidenaga Takahashi, Yukio Otobe, Kiyoshi Kohiyama ]
9. Low Power Consumption Digital Signal Processor:Hi-Perion (198 KB)
A low power consumption 16-bit fixed-point Digital Signal Processor (DSP) was developed for mobile handy terminals. Two MACs are employed and operated alternatively. This architecture enables high-speed processing at a low supply voltage, effectively reducing operating power. Compatibility of the firmware is maintained. An experimental chip consumed 11 mW at a 1.2 V Vdd when the PSI-CELP CODEC firmware was run at 40 MHz. ---[Teruo Ishihara, Shinya Kondou, Hideaki Fukuda ]

Circuit Technologies

10. A 0.9 V Low-power 16-bit DSP Based on a Top-down Design Methodology (212 KB)
A 0.9 V low-power (8.7 mW) 16-bit DSP was developed for mobile wireless use using a 0.25 µm dual-threshold-voltage (dual-Vth) CMOS process. To obtain a high-performance LSI at a low supply voltage and also to speed up the design process, we propose a new top-down design methodology in which iterations are done within the block synthesis step so that the layout can be fixed in one pass. There are four main design steps in the methodology. 1) Inter-block wires in the chip top level are routed and their precise delays are extracted from their shapes. Then, the locations of circuit blocks in the chip top level are optimized by performing timing analysis. 2) To synthesize the blocks, timing budgets are assigned according to the precise wire delays. 3) The block synthesis with the inter-block wire delays and re-assignment of the timing budgets for neighboring blocks are repeated until the timing budgets become feasible and consistent for the whole chip. 4) The entire chip layout, which involves placement and routing inside the blocks and detailed routing in the chip top level, is completed. As a result, no timing violation appears in the final timing analysis. . ---[Atsushi Tsuchiya, Tetsuyoshi Shiota, Shoichiro Kawashima ]
11.Dual-Vth 0.25 µm CMOS Cells and Macros for 1 V Low-power LSIs (253 KB)
Dual-threshold-voltage (dual-Vth) 0.25 µm CMOS 1 V cells and macros were developed which use a low Vth MOSFET to achieve high speed at a low voltage and a high Vth MOSFET to keep the leakage current low in standby mode. The line-up of 1 V characterized logic standard cells, a fast signal level converter, a 1 V-to-1.5 V supply voltage converter, and a 1 V SRAM and 1 V ROM consume on average 1/5 of the power consumed by their equivalents in a conventional 0.25 µm 2.5 V CMOS library yet are only 50% slower and have almost the same amount of leakage current in standby mode. ---[Isao Fukushi, Ryuhei Sasagawa, Wataru Shibamoto]
12. A 2-byte Parallel 1.25 Gb/s Interconnect I/O Interface with Self-configurable Link and Plesiochronous Clocking (289 KB)
An I/O transceiver for scalable multiprocessor systems has been developed with a high parallel bandwidth (1.25 Gb/s x 2-byte) and low latency (7.4 ns). The transceiver performs plesiochronous clocking, and compensates for skin-effect cable loss and inter-wiring skew across cable connections of 20 m in length. We used a phase-interpolator-based clocking scheme that ensures a high skew-adjustment resolution (25 ps ± 5 ps adjustment step) and plesiochronous clocking and can tolerate slight differences in frequency between the incoming and internal reference clocks. A Differential Partial Response Detection (DPRD) receiver has also been developed to ensure a low latency equalization for a skin-effect cable loss of up to 10 dB. The receivers are equipped with deskew circuitry to tolerate an inter-wiring skew of up to 6.4 ns for 20 data bits. The data rate, driver output level, and receiver clock phase are adjusted automatically by a logic sequencer called the "Basic control." The sequencer maximizes the data rate and the minimizes power consumption without external manual adjustments, and can adapt to a wiring environment ranging from on-board PCB traces to 20 m twisted-pair cables. We designed a test chip for parallel-link interconnection using a 0.25 µm CMOS process and confirmed that it was capable of 1.25 Gb/s 2-byte parallel signal transmission over a 20 m AWG 28 twisted-pair cable. ---[Kohtaroh Gotoh, Hideki Takauchi, Hirotaka Tamura ]

Device Process and Packaging Technologies

13. Process Technologies for SOCs (657 KB)
TThis paper introduces a family of process technologies for fabriating high-performance SOCs. These technologies can be used to embed digital and analog elements and memory such as SRAMs, ROMs, DRAMs, and flash EPROMs. Currently, any macro cell, except a flash EPROM, can be integrated on a silicon chip using the developed 0.25 µm and 0.18 µm process technologies. Although it is currently very difficult to assure full compatibility between flash EPROMs and other macro cells, these technologies enable a flaTaiji Ema ]
14. Advanced LSI Packaging Technologies (296 KB)
Mobile devices need to be small, and the packages of most chips have been miniaturized as much as possible in order to meet this need. The Chip Size/Scale Package (CSP) was realized in the 1990s, and Fujitsu, as one of the pioneers in this area, has supplied various CSPs. This paper describes the structure, characteristics, and reliability of Fujitsu's CSPs. Then, a package for high-speed devices is described. ---[Katsuro Hiraiwa, Masaharu Minamizawa ]

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