SPARC64 VI/VII/VII+ enhances the high performance and high reliability features of SPARC64 V and further boosts performance using multi-core and multi-thread per core technology imbedded on a single CPU chip. SPARC64 VII/VII+ has 4 cores per CPU chip, SPARC64 VI has 2 cores per CPU chip. Plus, SPARC64 VII+ reduces data access time by doubling level2 cache.
The multi-core, multi thread per core, and large on chip cache memory provides a significant boost over single chip performance.
Multi-threading technology minimizes CPU core wait times and increases CPU core utilization. In SPARC64 VII/VII+, SMT (Simultaneous Multithreading) enables two threads running in parallel. In SPARC64 VI, VMT(Vertical Multithreading) enables efficient thread execution.
A large level2 cache memory seriously shrinks memory latency.
SPARC64 high performance technologies such as super scalar, Out-of-Order execution, branch prediction and non-blocking cache are maintained.
SPARC Enterprise with high-performance SPARC64 VI/VII/VII+ chips provides supreme performance across a wide range of applications including large-scale transaction processing.
|SPARC64 VI||SPARC64 VII||SPARC64 VII+|
|CPU cores per chip||2||4||4|
|Threads per CPU core||2 (VMT)||2 (SMT)||2 (SMT)|
|Level1 cache||256KB with 2ways per core||128KB with 2ways per core||128KB with 2ways per core|
|Maximum Level2 cache||6MB with 12 ways at maximum (per CPU chip)||6MB with 12 ways at maximum (per CPU chip)||12MB with 12 ways (per CPU chip)|
Single chip performance is much improved by multi-core imbedding in the chip, with quad cores in SPARC64 VII/VII+ and dual cores in SPARC64 VI.
Multi-threading technology minimizes CPU core wait times, increases CPU core utilization. In SPARC64 VI/VII/VII+, dual threads per core are executed efficiently.
In single thread per core processors, instruction execution suspends during memory access and resumes after data read action is completed.
Such linear instruction processing takes time.
Using VMT mechanism in SPARC64 VI, when thread1/process 1 starts its memory access, instruction control is switched to thread2 and thread2/process 2 is executed. When thread2 starts its memory access, instruction control is switched back to thread1 and the suspended thread1/process 1 is resumed.
The two thread switching mechanism minimizes processor wait time, efficiently utilizes memory access time and maximizes the performance of SPARC Enterprise mid-range and high-end models.
Using SMT mechanism in SPARC64 VII/VII+, thread1 and thread2 run in parallel, minimizing processing time.
SPARC64 VI/VII/VII+ incorporates various high performance technologies including: Out of Order Execution: which starts instructions when they have executable data, and Branch Prediction Mechanism: which predicts and prepares for the most likely instruction sequence.