Memory interleave improves large memory access
SPARC Enterprise M3000 model and above use memory interleave technology. This improves memory access performance by enabling parallel access to multiple memory chips. This function is especially effective with applications that deal with large amounts of data.
In typical server systems, large contiguous memory access tends to be a performance bottleneck due to wait times caused by memory access latency.
The memory interleave function of SPARC Enterprise enables reading of large memory chips in parallel and reduces memory access times.
The memory interleave function accesses max 32 memory chips on a single CPU Memory Board, in parallel.