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System-on-a-Chip


FSTJ 2006-4 Cover Image

2006-4 (Vol.42, No.2)

In this special issue, we focus on the system-on-a-chip (SoC) for multimedia, network, and communication solutions. We also describe our new IDM (Integrated Device Manufacturer) business model that focuses on a partner relationship suitable for SoCs.
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2006-4 (Vol.42, No.2) Contents

1. Preface (24 KB)
The ongoing efforts to keep up with Moore's law and scaling rules have made it possible to integrate more than 100 million transistors on a single silicon chip, and we are witnessing the aggressive pursuit of 65 nm and 45 nm CMOS technologies throughout the world. This trend has enabled the integration of high-performance processor cores, large-size memories, and various functional blocks into a single chip called a system-on-a-chip (SoC). ---[Shinpei Hijiya, Member of the Board General Manager, System LSI Development Laboratories Fujitsu Laboratories Ltd.]
2. Summary of Fujitsu SoC Technology and Related Business (96 KB)
The system-on-a-chip (SoC) first appeared in the LSI market about 12 years ago. Since that time, continuous advances have been made in SoC process technology and design methodology. Given the increasing complexity of SoCs, the relationship between semiconductor vendors and customers has changed from a simple "sell & buy" relationship to one based on a more complex mutual dependency. This paper describes the recent general trends in SoC technology and business, along with Fujitsu's response to these trends. This paper also describes how Fujitsu plans to handle SoC and LSI business in the future. ---[Joji Murakami]

Multimedia

3. Mobile Multimedia Platform (MMP) (64 KB)
Mobile phones incorporating camera modules and music players are rapidly becoming popular not only in Japan, but throughout the world. This growth has led to stronger demands for mobile phones equipped with additional functions that offer graphics, audio, and images of higher quality. To fully meet these demands, we have constructed a mobile multimedia platform (MMP) based on an ARM processor with common intellectual properties (IPs). We used this platform to develop three system-on-a-chips (SoCs): the MB86V00, MB86V01, and MB86V02 (which incorporates audio/speech processing functions for the mobile phone market). These SoCs provide all the high-resolution camera/video functions required for mobile phones on a single chip with low power consumption. This paper describes the design concepts of the MMP, the development of these SoC products, and the SoCs' low-power consumption technology. ---[Kenichiro Kuroki]
4. FR-V Single-Chip Multicore Processor: FR1000 (246 KB)
To realize the low power consumption and low-cost equipment needed to decode high definition broadcasts, Fujitsu has developed a single-chip multicore processor FR1000 that integrates four 8-way, Very Long Instruction Word (VLIW) FR-V processor cores. This new multicore processor is fabricated using a 90 nm, nine-metal-layer CMOS process and a 900-pin flip-chip package. The processor cores operate at 500 MHz, the memory interfaces at 250 MHz, and system bus at 166 MHz. The use of a single processor core enables MPEG-2 MP@ML video-stream decoding at 190 MHz. Conversely, the use of four processor cores enables the decoding of MPEG-2 MP@HL video streams by just using software. Moreover, this new processor needs only about 3 W to decode MPEG-2 MP@HL video streams. This paper introduces the hardware and software development environment of this new processor, describes the processor's software operation environment, and cites some examples of its application. ---[Atsuhiro Suga, Satoshi Imai]

Network and Communication

5. Ultra-High-Speed CMOS Interface Technology (118 KB)
Enhancing the performance of the broadband Internet and the performance of computer and storage systems requires high-bandwidth networks to interconnect these systems. Fujitsu has already marketed high-speed network interface products such as the 10 G Ethernet and has recently developed a CMOS interface that accommodates high-speed data transfer at 6.4 Gb/s per signal line to increase network bandwidth. For this interface, we have developed a multi-tap pre-emphasis function for the transmitter and an adaptive equalizer for the receiver that can compensate for a high-frequency transmission loss of 20 dB or more in the backplane of devices and in cables that interconnect cabinets. When this CMOS interface is mounted on a system-on-a-chip (SoC) as a multi-channel interface, the system bandwidth can be upgraded significantly. This paper describes an ultra-high-speed CMOS interface that was manufactured experimentally using Fujitsu's 0.11 μm CMOS process. ---[Satoshi Matsubara, Hideki Ishida ,Kohtaroh Gotoh]
6. Single-Chip, 10-Gigabit Ethernet Switch LSI (196 KB)
To develop flexible, highly reliable IT systems, there is an emerging need to provide compact, low-cost, and low-latency 10-Gigabit Ethernet switches to interconnect high-speed servers and large storage systems. To meet this need, Fujitsu has developed the world's first single-chip, 10-Gigabit Ethernet switch LSI. This LSI features twelve 10-Gigabit Ethernet interface ports that support layer-2 switching functions. It has a newly developed I/O circuit called the enhanced 10-Gigabit Attachment Unit Interface (eXAUI) that can transfer 10-Gigabit Ethernet signals over a 25 m copper cable, making it possible to reduce the size, cost, and power consumption of IT systems. The chip has been incorporated into 10-Gigabit Ethernet switches that are now deployed in data centers and high-performance computing applications. This paper describes the key technologies of this LSI, its functions and structure, the eXAUI circuit, and the integration of its circuits. It also includes an evaluation of the LSI's performance and a brief description of a reference board for the LSI. ---[Takeshi Horie, Takeshi Shimizu, Akira Hattori]
7. High-Speed IP/IPsec Processor LSIs (134 KB)
In recent years, we have seen an increase in the speed of Internet access lines together with demands for concealed communications. To meet these demands, we have developed two LSIs, the MB86977 and MB86978, which are optimized for use in gateways such as broadband VPN routers for secure, high-speed communications. The MB86977 is a high-performance IP packet processing engine. After it has been programmed, this device can process bi-directional routing, Network Address Port Translation (NAPT), Point to Point Protocol over Ethernet (PPPoE), and filtering at a 100 Mb/s full-wire speed. The MB86978 is an IPsec accelerator LSI capable of processing packets inline on the transmission path. Once this device has been programmed, it can perform bi-directional IPsec processing at a 100 Mb/s full-wire speed. This paper describes the functions, performance, and mechanisms of these two LSIs. It then describes how these LSIs are superior to software processing solutions. Lastly, this paper introduces a reference board that can facilitate rapid development of broadband VPN routers. ---[Tomokazu Aoki, Teruhiko Nagatomo, Kazuya Asano]
8. System-on-a-Chip with Security Modules for Network Home Electric Appliances (156 KB)
Home electric appliances connected to the Internet and other networks allow users to easily access a variety of information and services. However, the users of such appliances are increasingly exposed to the threat of information leaks, unauthorized access, and other risks. Therefore, home electric appliances connected to networks must provide adequate security functions. This paper introduces three new Fujitsu system-on-a-chips (SoCs) developed for network home electric appliances. These SoCs provide network, security, and control functions for home electric appliances and peripheral components. The new SoCs can also provide these functions for a digital home system and process the data of the system's devices. Moreover, when connected to an existing system, they can be used as slave processors for network and security processing. ---[Hiroyuki Fujiyama]
9. Digital Content Protection LSI for PC-Based Digital TV Receivers (97 KB)
This paper describes a "digital content protection LSI" that prevents the hacking of PC-based digital TV receivers. Given the wide public knowledge about PC architecture, crackers may gain unauthorized access to PC software. Consequently, many broadcasters and other content holders are concerned that digital broadcast content may be stolen. This situation has curtailed the development of PC-based digital TV receivers for some time. Therefore, we have designed a protection scheme whereby content is protected even in open architecture environments such as the PC environment. This protection has been implemented in the form of a digital content protection LSI. These LSIs will open the way for the continued development of PC-based digital TV receivers. ---[Kiyoshi Kohiyama, Hiroyuki Fujiyama, Toshiyuki Yoshitake]
10. Single-Chip Baseband Signal Processor for Software-Defined Radio (146 KB)
Reconfigurable processor technology offers a way to couple significant hardware performance improvements with realtime software signal processing. This technology enables software-defined radio (SDR) to be realized on a system-on-a-chip (SoC) platform. In this paper, we describe an SDR SoC LSI that is suitable for use in programmable wireless communication systems. The LSI has two advanced features. First, the hybrid architecture consists of reconfigurable signal processors and accelerator circuits. These accelerators are parametric circuits essential for baseband processing. Second, the reconfigurable processing elements have a cluster structure that improves the mapping efficiency and minimizes the processing time. We also describe a prototype SDR system that uses this LSI to perform software-defined IEEE802.11a and 11b communications. ---[Seiichi Nishijima, Miyoshi Saito, Iwao Sugiyama]
11. 10-bit, 125 MS/s, 40 mW Pipelined ADC in 0.18 μm CMOS (175 KB)
This paper presents a 10-bit, 125 MS/s CMOS pipelined analog-to-digital converter (ADC). The power consumption of this ADC is just 40 mW at a supply voltage of 1.8 V, which is less than half that of other ADCs with an equivalent sampling rate. Low power consumption is achieved by using a flip-around digital-to-analog converter (FADAC) that reduces the power consumption of the front-end circuit by 50% compared to that of a conventional one. The ADC was fabricated using 0.18 μm CMOS technology, and the active area is 1.1 × 0.6 mm2. The measured peak signal-to-noise and distortion ratio (SNDR) is 54.2 dB with an 80 MHz input operating at a 125 MS/s sampling rate. The ADC will help reduce the power consumption of system-on-a-chips (SoCs) for digital consumer products and wireless communication equipment. ---[Masato Yoshioka, Masahiro Kudo]

Design Methodologies

12. CAD Tools for Early Timing Closure in System-on-a-Chip Design (64 KB)
This paper introduces two new CAD tools, "March" and "MagusMCP," developed to partially automate the design of clock signal distribution for timing optimization and the timing constraints for systems-on-a-chip. March synthesizes flexible structures of clock distribution circuits based on flip-flop (FF) grouping and placement information. It also considers the placement and routing resource information of RAM and optimizes the delay on clock paths and clock skew. These features make it easier to satisfy timing constraints. MagusMCP automatically detects multi-cycle/false paths based on analysis that takes circuit logic into account. These tools make it possible to ease timing constraints, thus enabling early timing closure. ---[Yuzi Kanazawa, Hiroyuki Higuchi]
13. LSI Noise Model for Power Integrity Analysis and Its Application (125 KB)
Semiconductor scaling is making power integrity inside system-on-a-chips (SoCs) a major design issue. To investigate this issue, we developed an LSI noise model and simulation methodology to analyze power integrity. Using this methodology, we can simulate power supply noise inside an LSI, for example, the simultaneous switching noise of I/O circuits and core noise caused by dynamic switching currents. We can also use this model in the initial design stage to optimize the power wiring and minimize the power pin-count and thereby minimize the chip cost. In this paper, we first describe the noise that must be considered when designing an LSI's power system. We then describe the structure and generation flow of the LSI noise model, the measurement results of a test chip we used for verifying the model's accuracy, and the application of the model in product development. ---[Tomio Sato, Tetsutaro Hashimoto, Ryuhei Sasagawa]

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