Reliability of UltraSPARC T2/T2 Plus processor
UltraSPARC T2/T2 Plus processors have high-level RAS functions (Reliability, Availability, Serviceability). Data in level1
cache memory is protected by parity check and level2 cache memory and registers by ECC.
If correctable errors occur frequently, failed parts are deactivated by core unit, preventing uncorrectable errors.
SPARC Enterprise entry models using UltraSPARC T2/T2 Plus provide highly reliable systems.
| Error detection | Error correction | |
|---|---|---|
| Level1 cache memory | Parity | Retry |
| Level2 cache Memory | ECC | ECC |
| Register | ECC | ECC |
Advanced RAS functions improve business continuity
Data protection mechanisms in cache memory
For protecting cache memories of high dense circuits (*1) from soft errors, data protection mechanisms are embedded across cache memory.
Level1 cache is protected by parity check and level2 cache by ECC. If a one-bit error occurs in level1 cache, data is re-read from level2 cache and processed again. After such retrying, if correctable errors occur frequently, failed parts are deactivated by core unit, preventing unrecoverable errors.
*1 Soft error is temporary data error which occurs regardless of hardware status due to external environment such as radiation etc.
Register data protection
With ECC mechanism, data in integer and floating point registers is assured.
Cache scrubber
Cache scrubber is a hardware function that checks for errors in level2 cache memory. If a one-bit error occurs, the error is recovered.
