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ASIC Documentation

  • .11µm Standard Celll Fact Sheet (151KB PDF)

    Fujitsu's CS91, a 110nm (70nm Leff ) standard-cell product, is based on Fujitsu's state-of-the-art CMOS process technology, a deep sub-micron process designed for today's high-speed and low-power SOC products. The cell library, which is optimized for synthesis-based designs, has accurate timing and power-characterized data, cell areas, and statistical wire-load models.

  • .13µm node CMOS Process (CS90A) Fact Sheet (90KB PDF)

    130nm node CMOS Process (CS90A) features and technology roadmap

  • .18µm Embedded Array Fact Sheet (97KB PDF)

    Fujitsu’s CE81 is a series of high performance, 0.18µm (0.13µm Leff) CMOS embedded arrays that include full support of diffused high-speed RAMs, ROMs, analog, mixed-signal macros, and a variety of embedded functions.

  • .18µm node CMOS Process (CS80B) Fact Sheet (77KB PDF)

    Features: 2-Poly and 6-Metal Process, Retrograde Twin Wells on P Epi Substrate, STI(Shallow Trench Isolation), Salicided Gate, Salicided Source and Drain, CMP Planarization, CVD Filling for Via, Stackable Contact and Vias, Oxide/Nitride Passivation

  • .18µm Standard Cell Fact Sheet (81KB PDF)

    Fujitsu’s CS81, a 0.18µm (0.13µm Leff) standard-cell product, is based on Fujitsu’s state-of-the-art CMOS process technology, a deep sub-micron process designed for today’s high-density and low-power SOC products. The cell library, which is optimized for synthesis-based designs, has accurate timing and power-characterized data, cell areas, and statistical wire-load models. The CS81 standard-cell library contains both high-performance and high-density cells, giving designers the option of combining both types of standard cell blocks on the same chip. The CS81 library supports popular third-party tools and data-exchange file standards.

  • .25µm Embedded Array Fact Sheet (156KB PDF)

    Fujitsu’s CE71 is a series of high-performance, 0.18µm Leff CMOS embedded arrays that include full support of diffused high-speed RAMs, ROMs, mixed-signal macros, and a variety of other embedded functions.

  • .25µm Standard Cell Fact Sheet (147KB PDF)

    Fujitsu’s CS71, a 0.25µm (0.18µm Leff) standard cell product, is based on Fujitsu’s state-of-the-art CMOS process technology–a process designed for high performance and high integration. The CS71 family offers up to 10 million
    gates, using as many as five layers of metal.

  • "Going, Going, Gone-- Is there a place for second-tier ASIC suppliers?" ASIC and SoC Strategies Article

    Article Table of Contents

  • 0.11µm CMOS Standard Cell Fact Sheet

    Fujitsu's CS91, a 110nm (70nm Leff ) standard-cell product, is based on Fujitsu's state-of-the-art CMOS process technology, a deep sub-micron process designed for today's high-speed and low-power SOC products. The cell library, which is optimized for synthesis-based designs, has accurate timing and power-characterized data, cell areas, and statistical wire-load models. The CS91 standard-cell library contains both high-performance and high-density cells, giving designers the option of combining both types of standard cell blocks on the same chip. The CS91 library supports popular third-party tools and data-exchange file standards. The CS91 chip cores can operate at 0.8V to 1.3V range. The I/Os, operating at 0.8V to 3.6V range, can conveniently interface with various types of devices. Interface options include low-swing, high-speed I/Os and high-speed
    bus interface I/Os.

  • 10/100 Mbps Ethernet MAC Core Fact Sheet

    The 10/100 MAC core is part of the Fujitsu IPWare™ Library. The 10/100 MAC core is a PAUSE Flow Control Ethernet Media Access Controller (MAC) capable of both 10 and 100 Mbps data operation.

  • 2.5Gbps Transceiver Macro with CDR Fact Sheet

    Fujitsu’s triple mode parallel transceiver is a physical I/O interface macro for ASICs that performs high-speed back plane data communication, operating at low power dissipation. The triple data transfer rates, 2.5G/1.25G/622M bps, can be selected depending on the system requirements.The
    macro consists of a 16-bit transmitter, and a 16-bit receiver array.The receiver macro contains CDR (Clock Data Recovery) using dual loop PLL (analog and digital PLL), that complies with SONET/SDH jitter tolerance mask, up to 72-bit run length.The Receiver has an integrated line equalization
    capability to compensate for inter-symbol-interference (ISI), which enables a wide variation in data link length and range, from short PCB trace to long twisted pair cables connections.The device also includes on-chip PRBS generators and comparators for testability.

  • 2.5Gbps Transceiver Macro with CDR Fact Sheet (90KB PDF)

    Fujitsu’s triple mode parallel transceiver is a physical I/O interface macro for ASICs that performs high-speed back plane data communication, operating at low power dissipation. The triple data transfer rates, 2.5G/1.25G/622M bps, can be selected depending on the system requirements.The macro consists of a 16-bit transmitter, and a 16-bit receiver array.The receiver macro contains CDR (Clock Data Recovery) using dual loop PLL (analog and digital PLL), that complies with SONET/SDH jitter tolerance mask, up to 72-bit run length.The Receiver has an integrated line equalization capability to compensate for inter-symbol-interference (ISI), which enables a wide variation in data link length and range, from short PCB trace to long twisted pair cables connections.The device also includes on-chip PRBS generators and comparators for testability.

  • 2007.5 Product Guide [ASSP/Memory/ASIC]
  • 3.125Gbps Parallel CDR Transceiver (0.11µm) Fact Sheet (64KB PDF)

    Fujitsu’s parallel transceiver, is a seletable 2/4/8/16- channel CDR receiver and transmitter array intended for ASICs that perform at high bandwidth data
    communications.

  • 3.125Gbps Parallel CDR Transceiver (0.18µm) Fact Sheet (417KB PDF)

    Fujitsu’s parallel transceiver, which is available in 2/4/8/16-channel width CDR receiver and transmitter arrays, is for ASICs that perform at high bandwidth data
    communications. The macro meets SONET/SDH OC-48 jitter tolerance mask requirement. The macro has 175mW/ch power dissipation (including Rx, Tx, CDR, bias circuit and PLL, maximum pre-emphasis, 16ch case) and runs under power
    supply of 1.8V±0.15V, 3.3V±0.30V and junction temperature of -40°C ~ 125°C.

  • 3.125Gbps x 4 Parallel Transceiver (0.11µm) Fact Sheet (98KB PDF)

    The Fujitsu’s XAUI macro is for ASICs that perform at
    high bandwidth data communication.

  • 3.125Gbps x 4 Parallel Transceiver (0.18µm) Fact Sheet (53KB PDF)

    The Fujitsu’s XAUI macro is for ASICs that perform at high bandwidth data communication.

  • 90nm CMOS Standard Cell Fact Sheet (71KB PDF)

    CS101 Series, a group of 90nm standard cells, addresses the design challenges of the mobile device market in which low power consumption and multifunctionality are required. Also, the CS101 products serve the design needs of the leading-edge network devices, server applications and telecommunication equipment markets where high performance is vital.

  • 90nm node CMOS Process (CS100A) Fact Sheet (276KB PDF)

    90nm node CMOS Process (CS100A) features and technology roadmap

  • ARC Processor Core Fact Sheet

    ARC is comprised of a Base RISC Engine, the ARC Extension Library, the Architect, integrated test suites, multi-interface architecture, the ARC Co-design toolset, a complete software development toolchain, and both hardware
    and software emulators. Provided as a synthesizable “soft macro‿with the configuration controlled by the user through the ARC Architect test suite, the ARC architecture can be configured to meet specific performance and cost targets
    enabling customers to effectively manage their design process at the system level.

  • ARM7TDMI™ Processor Core Fact Sheet

    The ARM7TDMI embedded CPU core is part of Fujitsu’s IPWare™ Library. The Fujitsu ARM7TDMI processor core, developed by ARM, is implemented in Fujitsu’s 0.25µm process technology. This core contains all of the ARM7TDMI processor features, including a 32-bit RISC engine, Thumb instruction set (smaller code size), debug functions, multiplier, and embedded ICE support logic. The ARM7TDMI processor is supported by multiple hardware and software vendors through a wide array of development tools and RTOS created by ARM.

  • ASIC Mixed-Signal and Analog Macros Fact Sheet (159KB)

    To achieve the highest level ofsystem integration, Fujitsu offers avariety ofanalog and mixed-signal macros for customer use inconjunction with its Embedded Arrays and Standard Celllibraries. Data communications, networking, graphics, anddigital audio/video are among the applications that can takeadvantage ofthese mixed-signal and analog macros. Additionally,embedded RAMs, ROMs, phase-locked loops (PLLs), and otherSOC IP cores from Fujitsu’s IPWare™are provided to enablecustomers to implement system-level solutions on a single chip.

  • ASIC Packaging Article

    For its ASIC customers, Fujitsu offers "one-stop shopping" for all their packaging needs. In addition to a robust set of off-the-shelf standard packages, Fujitsu offers complete inhouse turnkey package design, as well as assembly and test services. Fujitsu’s ASIC packaging solutions range from lead insertion matrix-type PGAs to surface mount Flat Quad \Lead types (QFP, LQFP, TQFP, HQFP) and Matrix types (BGAs and LGAs).

  • Bluetooth™ Solution Article

    BluetoothTM is a standard for radio communication over short distances on the
    2.4GHz band. This article introduces the features of our BluetoothTM solution
    for embedded devices that conform to BluetoothTM version 1.1.

  • Bluetooth™ Solution BlueA™

    Products Outline, Fujitsu Solutions for customer applications, Block Diagram

  • CE61 Series Embedded Array Fact Sheet

    Fujitsu’s CE61 is a series of high-performance, CMOS embedded arrays featuring full support of mixed-signal macros, as well as diffused high-speed RAMs, ROMs and a variety of other embedded functions. The CE61 series offers density and performance approaching standard cells, yet provides the time-to-market advantage of gate arrays. The E-series is optimized for pad-limited designs, and the F-series offers a cost-effective solution for core-limited designs. A fifth
    metal layer option is also available for area bump designs, providing over 1,000 I/O pads.

  • Fujitsu SOC (Presentation)

    The Fujitsu Advantage, Fujitsu Solution Platform, IPWare Library, Example of SOC Engagement Model, Methodology and Tools

  • Fujitsu System Applications Support (Presentation)

    SOC Application Development Lab, Multimedia- VolP, Wireless-Bluetooth, Processors, DSP, and Peripherals- ARM Reference Platform

  • Fujitsu VoIP

    Custom-designed voice DSP •Consumer applications •Highly scalable •Single & multiple channels •High performance •Low power •Synthesized for: 0.25µm, 0.18µm, 0.11µm

  • High Performance ASIC Solutions for the Metro & Long Haul Markets (Presentation)

    Business Strategy, Target Markets, Products- Process Technology, Packaging Roadmap, High-Speed I-O Offerings Current Advanced ASICs, Case Study

  • High-speed Interface Technology for Image Data Transmission (332KB PDF)

    Fujitsu Find Magazine: Vol.26 No.1 2008

  • IP-Phone Chip Fact Sheet

    Fujitsu’s IP-Phone chip offers a comprehensive software package with a reference design that provides a complete and cost-effective solution. This fully integrated solution has a DSP engine, RISC host processor, Ethernet switch, and a rich set of peripherals. It simultaneously supports multiple channels of voice and fax and runs any combination of speech Vocoder algorithms, telephony functions, and fax relay. The DSP core is based on a customized RISC-DSP combo core, along with a hardware accelerator (co-processor) for performance enhancements.

  • LCOS Backplane Process Fact Sheet (117KB PDF)

    LCOS Backplane Process features, CMOS Image Sensor Process features, High Voltage Process

  • MB86C00/MBG011 Bluetooth™ Baseband LSI Fact Sheet

    MB86C00/MBG011 BluetoothTM Baseband LSI provides all the digital base band signal processing and protocol hardware to complement the functionality of external BluetoothTM RF IC.

  • PCI Peripheral Core Fact Sheet

    The PCI Synthesizable Core is a part of the Fujitsu IPWare™ Library. The Fujitsu PCI Cores are RTL synthesizable modules that provide an interface between an application and the PCI bus. All PCI protocol and timing requirementsare handled by the core, which is controlled through a simple application interface.

  • SERDES Framer Interface Level-4 Fact Sheet (38KB PDF)

    Fujitsu's SFI4-1.0 macro enables the interface of any two chips at an aggregate of 10 to 12.5Gbps in each direction. Sixteen 622/780 Mbps differential data lines (plus one clock) are provided in the transmit direction, and another sixteen
    (plus one clock) in the receive direction.

  • SERDES Framer Interface Level-5 Fact Sheet (47KB PDF)

    Fujitsu’s SFI-5 compliant transceiver macro is a 17- channel physical I/O interface macro for ASICs that perform high bandwidth data communication while operating at low power consumption. The transceiver consists of a 17-channel transmitter unit, a 17-channel receiver unit and a bias unit. The transmitter and the receiver are compliant with OIF SFI-5 specification.

  • SoC Design Environment RDF V3.0 that Supports Low-power Designs (312KB PDF)

    Fujitsu Find Magazine: Vol.26 No.1 2008

  • System Packet Interface Level-4 Fact Sheet (31KB PDF)

    The SPI-4 interface core enables the interconnection of physical layer devices to link layer devices in 10Gb/s POS, ATM, and Ethernet applications.

  • USB 2.0 Device Controller Macro Fact Sheet

    – Link
    • Protocol Engine (UDC-20) is a fully synthesizable soft core that supports high-speed (480 Mbps), full-speed (12Mbps) and low-speed (1.5Mbps) signaling bit rates.
    • UTMI (USB 2.0 Transceiver Macrocell Interface) enables connection with discrete PHY chip (ASSP) as well as integrated PHY.
    • Protocol engine reduces CPU burden by processing basic USB 2.0 protocols in hardware.

  • USB Function Core Fact Sheet

    The USB Function Core is a synthesizable core and is part of the Fujitsu IPWare™ Library. This core is fully compliant with revision 1.0 of the USB specification.

  • USB Host Controller Core Fact Sheet

    The USB Host Controller is a synthesizable core and is part
    of the Fujitsu IPWare™ Library.

  • Utopia Level II / I Interface Core Fact Sheet

    The Utopia Level II interface provides a standard interface between a single ATM layer device and multiple PHY layer devices. The macro can also be configured as a Utopia Level 1 interface, which is used to provide a standard interface between a single ATM layer device and a single PHY layer device. The macro may be used in either ATM Layer or PHY Layer mode. Eight or 16-bit Utopia data is supported. The macro also performs data flow control between the two layers: parity checking and port address/poll address routing.

  • VOIP CODEC Fact Sheet

    VoIP Codec is designed for implementing speech Vocoders to support VOIP applications for Customer Premises Equipment (CPE). Up to 4 channels of audio can be supported simultaneously. The current implemented Vocoders are G.711, G.726, G.728, G.729AB, and G.729E. Any combination of Vocoders is supported and each channel provides echo cancellation (G.168), DTMF generation/detection, and jitter buffering. The DSP engine is based on ARC-3 Processor utilizing its DSP
    extensions together with extensive hardware accelerators (Co-Processor). This provides a flexible and powerful soft solution for future algorithm enhancements and upgrades. Test chip is offered as a Soft Core Silicon for ASIC & SOC designs. A top-level block diagram of the chip is shown above.

AccelArray Documentation

  • AccelArray IP-Rich Platform for Optimized Functionality, Performance and Time to Market (Article)

    AccelArray IP-rich platforms enable users to significantly improve their time-to-market and lower the total cost of ownership when designing complex, applicationspecific system-on-chip (SoC) products compared to conventional
    ASICs.

  • AccelArray Mega Platforms Fact Sheet

    AccelArray™ is an innovative technology and design approach that leverages Fujitsu’s ASIC design experience, system-level expertise and commitment to offer unprecedented performance with a short time to market. Additionally, AccelArray offers significantly lower up front NRE costs compared to cell-based ASICs in 0.11µm technology. The architecture eliminates many design tasks that consume a considerable amount of time in back-end physical design, such as DFT insertion, power mesh and clock tree synthesis. In addition, internal timing closure, cross talk analysis and corrections, and I/O timing closure are extremely simplified. AccelArray's unique architecture offers the lowest power solution in its class. Power dissipation is significantly improved, over similar solutions, through the use of embedded Flip Flops, pre-defined clock tree architecture
    and optimized libraries for gate density and lower power.

  • AccelArray- Performance like ASIC, Time-to-market like FPGA with Ideal Development Cost (Presentation)

    Market Opportunity, AccelArray- Value Advantage, Features, Architecture, Target Vertical Markets, Summary

  • AccelArray Technology Reduces ASIC Costs and Turnaround Times, and Offers 400 Mbps DDR Interface (The Syndicated)
  • AccelArray Technology Update (Article)

    Innovative technology that addresses design challenges in 0.11µm technology
    with low non-recurring engineering costs and fast turn-around time

  • AccelArrayTM Giga Platforms Fact Sheet

    Giga platforms address the specific needs of mid-volume vertical markets that require the performance of cell-based ASICs. These platforms leverage Fujitsu's decades of ASIC design and system-level expertise in the networking, storage
    networking, next-generation consumer electronics and imaging markets.

Broadband Wireless Access_WiMAX

Microcontrollers Documentation

8 Bit Series

16 Bit Series

FR32 Bit Series

Biometric Sensors Documentation

  • 2007.5 Product Guide [ASSP/Memory/ASIC]
  • Biometric Sensor Part Number Description

    Part Numbering Guide

  • DKF 200-USB Software Development Kit Fact Sheet

    The DKF200 Software Development Kit combines USB v1.1 with a Windows 98, 2000 compatible minutia based fingerprint matching engine to yield world class fingerprint authentication performance.

  • MBF200 Solid State Fingerprint Sensor Data Sheet

    The Fujitsu MBF200 Solid-State Fingerprint Sensor is a direct contact, fingerprint acquisition device. It is a high performance, low power, low cost, capacitive sensor composed of a two dimensional array of metal electrodes in the sensing array. Each metal electrode acts as one plate of a capacitor and the contacting finger acts as the second plate. A passivation layer on the device surface forms the dielectric between these two plates. Ridges and valleys on the finger yield varying capacitor values across the array, and the resulting varying discharge voltages are read to form an image of the fingerprint.

  • MBF200 Solid-State Fingerprint Sensor Fact Sheet

    The Fujitsu MBF200 is a 500 DPI 8-bit grayscale solid-state fingerprint sensor that reliably captures fingerprint information. The MBF200 is designed to integrate into
    devices for improved security and convenience. Applications for the MBF200 include: computer and network logon, physical access control, Point-of-Sale terminals, transportation security, medical information protection, cardholder ID validation and many other uses. The Fujitsu MBF200 provides a reliable, quick and user-friendly alternative to passwords, PIN's and other forms of user authentication.

  • MBF310 Solid-State Fingerprint Sweep Sensor Fact Sheet

    The MBF310 is a small, capacitive-based fingerprint Sweep
    Sensor™that is designed to easily add biometric security to
    today’s mobile devices such as cellular phones, PDA’s and other
    hand-held devices. The MBF310 is optimized to meet the
    demanding size, power and cost requirements of small,
    battery-operated devices that contain personal data and/or
    are connected to private networks.

  • Simple Fingerprint-Based Security Protects Notebook PCs Technology Backgrounder

    Lost or stolen notebook computers make headlines when they contain personal information on millions of people or data from nuclear weapons research. More quietly, corporations are becoming increasingly alarmed by the loss of notebooks that contain company-confidential information and enable access to corporate networks.

  • SPF200-USB Fingerprint Sensor Fact Sheet

    The Fujitsu SPF200-USB is an all-in-one USB device. Simply connect it to your USB cable and you have a working fingerprint sensor! The SPF200-USB is ideal for integrating into devices where USB is the communication interface such as computer peripherals and embedded applications. Mount the SPF200-USB into your device and you have a completed product without going through the expense of board layout and debug.

Networking ASSP Documentation

Wireless ASSP Documentation

DAC

  • 2-Channel DC/DC Converter IC with Overcurrent Protection MB39A104 Fact Sheet

    This 2-channel DC/DC converter IC utilizes the pulse width modulation type
    (PWM method) and features a built-in timer latch overcurrent protection circuit
    (no current sense resistor is necessary). Since it is capable of operation
    at high frequency, the coil value can be relatively small.
    This converter is optimal for the built-in power supply such as LCD monitors.

  • 4-Channel DC/DC Converter IC with Support for Low Voltage MB39A103 Fact Sheet

    A 4-channel DC/DC converter IC with pulse width modulation type
    (PWM method) while achieving support for low voltage startup (1.7V～).
    Four built-in channels in a TSSOP-30P/BCC-32P package enable control and
    soft-startup on each channel.

  • DK86060-3 16-Bit Interpolating DAC Development Kit

    Fujitsu’s DK86060-3 16-bit Interpolating DAC Development Kit provides a simple and effective means of evaluating the MB86060. This enables faster device evaluation without incurring the time and cost penalties of in-house PCB design and manufacture.

  • DK86061-3 12-Bit 400MSa/s DAC Development Kit

    Fujitsu’s DK86061-3 12-bit 400MSa/s DAC Development Kit provides a simple and effective means of evaluating the MB86061. This enables faster device evaluation without incurring the time and cost penalties of in-house PCB design and
    manufacture.

  • High Performance CMOS Digital to Analog Converters Fact Sheet

    The MB86060 is a high performance, 12-bit, 400 MSa/s Digital to Analog Converter (DAC) with a 16-bit interpolation filtering front-end. Fujitsu’s proprietary architecture (patent pending) delivers high speed with low
    power consumption.

  • MB86060 16-Bit Interpolating Digital to Analog Converter Product Flyer

    The Fujitsu MB86060 is a high performance 12-bit, 400MSa/s Digital to Analog Converter (DAC) enhanced with a 16-bit interpolation filtering front-end. Use of novel techniques for the converter architecture delivers high speed operation consistent with BiCMOS or bipolar devices but at the low power of CMOS. Fujitsu’s proprietary architecture is the subject of several patent applications. Additional versatility is provided by selectable input interpolation filters, programmable dither and noise shaping facilities. Excellent SFDR performance coupled with high speed conversion rate and low power make this device particularly suitable for high performance communication systems, in particular direct IF synthesis applications.

  • MB86061 12-Bit 400MSa/s Digital to Analog Converter

    The Fujitsu MB86061 is a high performance 12-bit 400MSa/s digital to analog converter (DAC). Use of novel techniques for the converter architecture delivers high speed operation consistent with BiCMOS or bipolar devices but at the low power of CMOS. Fujitsu’s proprietary architecture is the subject of several patent
    applications. Excellent SFDR performance coupled with high speed conversion rate and low power make this device particularly suitable for high performance communication systems, graphics and test/instrumentation equipment applications.

  • Wireless ASSP Part Number Guide

PLL

  • 2-Channel DC/DC Converter IC
    with Overcurrent Protection
    MB39A104 Fact Sheet

    This 2-channel DC/DC converter IC utilizes the pulse width modulation type (PWM method) and features a built-in timer latch overcurrent protection circuit (no current sense resistor is necessary). Since it is capable of operation at high frequency, the coil value can be relatively small. This converter is optimal for the built-in power supply such as LCD monitors.

  • 2-Channel DC/DC Converter IC
    with Overcurrent Protection
    MB39A104 Fact Sheet

    A 4-channel DC/DC converter IC with pulse width modulation type
    (PWM method) while achieving support for low voltage startup (1.7V～). Four built-in channels in a TSSOP-30P/BCC-32P package enable control and soft-startup on each channel.

  • 3-Channel DC/DC Converter IC
    MB39A112 Fact Sheet

    3-channel DC/DC converter IC with maximum oscillation frequency of 2.6MHz utilizing the pulse-width modulation method. Three channels are built into the TSSOP-20P package, enabling control and soft-start for each channel and making it an optimal built-in power supply for ADSL modems, etc.

  • ASSP Dual Serial Input PLL Frequency Synthesizer MB15U30SP Fact Sheet

    The Fujitsu MB15U30SP is a serial input Phase Locked Loop (PLL) frequency synthesizer with 2.5GHz and 510MHz prescalers. A 32/33 or a 64/65 for the 2.5GHz prescaler, and a 8/9 or a 16/17 for the 510MHz prescaler can be selected that enables pulse swallow operation.

  • Built-in IF Band Voltage Controlled Oscillator, Mask ROM Frequency Synthesizer
    MB15C700 series Datasheet

    MB15C700 series is a Phase Locked Loop (PLL) frequency synthesizer of pulse swallow operation with built-in VCO suitable for Intermediate Frequency band synthesizer of mobile phones.

  • Dual Serial Input PLL Frequency Synthesizer (Small Package) MB15F72UV Fact Sheet

    The Fujitsu MB15F72UV is a serial input Phase Locked Loop (PLL) frequency synthesizer with a 1300MHz and a 350MHz prescalers. A 64/65 or a 128/129 for the 1300MHz prescaler, and a 8/9 or a 16/17 for the 350MHz prescaler can be selected for the prescaler that enables pulse swallow operation.

  • Dual Serial Input PLL Frequency Synthesizer (Small Package) MB15F73UV Fact Sheet

    The Fujitsu MB15F73UV is a serial input Phase Locked Loop (PLL) frequency synthesizer with a 2250MHz and a 600MHz prescalers. A 64/65 or a 128/129 for the 2250MHz prescaler, and a 8/9 or a 16/17 for the 600MHz prescaler can be selected for the prescaler that enables pulse swallow operation.

  • Dual Serial Input PLL Frequency Synthesizer (Small Package) MB15F74UV Fact Sheet

    The Fujitsu MB15F74UV is a serial input Phase Locked Loop (PLL) frequency synthesizer with a 4000MHz and a 2000MHz prescalers. A 64/65 or a 128/129 for the 4000MHz prescaler, and a 32/33 or a 64/65 for the 2000MHz prescaler can be selected for the prescaler that enables pulse swallow operation.

  • Dual Serial Input PLL Frequency Synthesizer (Small Package) MB15F76UV Fact Sheet

    The Fujitsu MB15F76UV is a serial input Phase Locked Loop (PLL) frequency synthesizer with a 6000MHz and a 1500MHz prescalers. Both IF and RF PLL section have a 1/4 divider. And a 16/17 or a 32/33 for the 6000MHz prescaler, and a 4/5 or a 8/9 for the 1500MHz prescaler can be selected for the prescaler that enables pulse swallow operation.

  • Dual Serial Input PLL Frequency Synthesizer MB15F02L Datasheet

    The Fujitsu MB15F02L is a serial input Phase Locked Loop (PLL) frequency synthesizer with a 1.2 GHz and a 250 MHz prescalers. A 64/65 or a 128/129 for the 1.2 GHz prescaler, and a 16/17 or a 32/33 for 250 MHz prescaler can
    be selected that enables pulse swallow operation.

  • Dual Serial Input PLL Frequency Synthesizer MB15F02SL Datasheet

    The Fujitsu MB15F02SL is a serial input Phase Locked Loop (PLL) frequency synthesizer with a 1200 MHz and a 500 MHz prescalers. The 1200 MHz and 500 MHz prescalers have a dual modulus division ratio of 128/129 or 64/65, and a 8/9 or a 16/17 enabling pulse swallowing operation.

  • Dual Serial Input PLL FrequencySynthesizer MB15F03L Datasheet

    The Fujitsu MB15F03L is a serial input Phase Locked Loop (PLL) frequency synthesizer with a 1800MHz and a 250MHz prescalers. A 64/65 or a 128/129 for the 1800MHz prescaler, and a 16/17 or a 32/33 for 250MHz prescaler can be selected that enables pulse swallow operation.

  • Dual Serial Input PLL Frequency Synthesizer MB15F03SL Datsheet

    The Fujitsu MB15F03SL is a serial input Phase Locked Loop (PLL) frequency synthesizer with a 1750 MHz and a 600 MHz prescalers. The 1750 MHz prescaler, and 600 MHz prescaler have a dual modulus division ratio of 64/65 or 128/129 and 8/9 or 16/17 enabling pulse swallow operation.

  • Dual Serial Input PLL Frequency Synthesizer MB15F05L Datasheet

    The Fujitsu MB15F05L is a serial input Phase Locked Loop (PLL) frequency synthesizer with a 1800MHz and a 233.15MHz prescalers. A 64/65 or a 128/129 for the 1800MHz prescaler, and a 16/17 for the 233.15MHz prescaler can be selected that enables pulse swallow operation.

  • Dual Serial Input PLL Frequency Synthesizer MB15F07SL Datsheet

    The Fujitsu MB15F07SL is a serial input Phase Locked Loop (PLL) frequency synthesizer with two 1100 MHz prescalers. The two 1100 MHz prescalers have a dual modulus division ratio of 128/129 or 64/65 enabling pulse swallowing operation.

  • Dual Serial Input PLL Frequency Synthesizer MB15F08SL Datsheet

    The Fujitsu MB15F08SL is a serial input Phase Locked Loop (PLL) frequency synthesizer with a 2500 MHz and a 1100 MHz prescalers. The 2500 MHz prescaler, and 1100 MHz prescaler have a dual modulus division ratio of 32/ 33 or 64/65 and 16/17 or 32/33 enabling pulse swallow operation.

  • Dual Serial Input PLL Frequency Synthesizer MB15F72UL Datasheet

    The Fujitsu MB15F72UL is a serial input Phase Locked Loop (PLL) frequency synthesizer with a 1300 MHz and a 350 MHz prescalers. A 64/65 or a 128/129 for the 1300 MHz prescaler, and a 8/9 or a 16/17 for the 350 MHz prescaler can be selected for the prescaler that enables pulse swallow operation.

  • Dual Serial Input PLL Frequency Synthesizer MB15F74UL Datasheet

    The Fujitsu MB15F74UL is a serial input Phase Locked Loop (PLL) frequency synthesizer with a 4000MHz and a 2000MHz prescalers. A 64/65 or a 128/129 for the 4000MHz prescaler, and a 32/33 or a 64/65 for the 2000MHz prescaler can be selected for the prescaler that enables pulse swallow operation.

  • Dual Serial Input PLL Frequency Synthesizer MB15F76UL Datasheet

    The Fujitsu MB15F76UL is a serial input Phase Locked Loop (PLL) frequency synthesizer with a 6.0 GHz and a 1.5 GHz prescalers. Both prescalers for RF and IF have a 1/4 divider. A 16/17 or a 32/33 for the 6.0 GHz prescaler, and a 4/5 or a 8/9 for the 1.5 GHz prescaler can be selected for the prescaler that enables pulse swallow operation. The BiCMOS process is used, as a result a supply current is typically 8.5 mA at 3.0 V. The supply voltage range is from 2.5 V to 3.6 V. A refined charge pump supplies well-balanced output current with 1.5 mA and 6 mA selectable by serial date. The pin assignments are is the same as the MB15F78UL. Fast locking is achieved for adopting the new circuit.

  • Dual Serial Input PLL Frequency Synthesizer MB15F78UL Datasheet

    The Fujitsu MB15F78UL is a serial input Phase Locked Loop (PLL) frequency synthesizer with a 2600 MHz and a 1200 MHz prescalers. A 32/33 or a 64/65 for the 2600 MHz prescaler, and a 16/17 or a 32/33 for the 1200 MHz prescaler can be selected for the prescaler that enables pulse swallow operation.

  • Dual Serial Input PLL Frequency Synthesizer On-Chip 1.1 GHz Prescaler MB15U10 Fact Sheet

    The Fujitsu MB15U10 is a dual serial input phase-locked loop (PLL) frequency synthesizer and is ideally suitable for mobile communications such as cellular phones.

  • Fractional-N PLL Frequency Synthesizer MB15F83UL Datasheet

    The Fujitsu MB15F83UL is Fractional-N Phase Locked Loop (PLL) frequency synthesizer with fast lock up function.

  • Fractional-N PLL Frequency Synthesizer MB15F86UL Datasheet

    The Fujitsu MB15F86UL is Fractional-N Phase Locked Loop (PLL) frequency synthesizer with fast lock up function.

  • Fractional-N PLL Frequency Synthesizer MB15F88UL Datasheet

    The Fujitsu MB15F88UL is Fractional-N Phase Locked Loop (PLL) frequency synthesizer with fast lock up function.

  • Fractional-N PLL Product Highlights

    The power current of each device is set according to its maximum operating frequency in order to accommodate a variety of cellular telephone systems (GSM, W-CDMA, TDMA, etc.).

  • IF Band PLL Frequency Synthesizer MB15C101Datasheet

    The Fujitsu MB15C101 is an exclusive Intermediate Frequency (IF) band Phase Locked Loop (PLL) frequency synthesizer with pulse swallow operation. The reference divider and comparison divider have fixed divide ratios, so that it is not required to set the divide ratios by a microcontroller externally.

  • IF Band PLL Frequency Synthesizer MB15C103 Datasheet

    The Fujitsu MB15C103 is an exclusive Intermediate Frequency (IF) band Phase Locked Loop (PLL) frequency synthesizer with pulse swallow operation. The reference divider and comparison divider have fixed divide ratios, so that it is not required to set the divide ratios by a microcontroller externally.

  • MB15Cxxx Series Low Voltage Integer Single PLL Frequency Synthesizers Fact Sheet

    The 0.35-micron CMOS MB15C100 IF series PLLs are for use in cellular handsets and pagers. They have low voltage & low current requirements while achieving a
    high level of performance. The MC15C100 is Mask Programmed to customer specified requirements. The MB15C101 and MB15C103 are standard products,
    factory set for popular IF frequencies. The MB15C101 is ideal for PHS systems and the MB15C103 for PDC systems. They are available in an 8-pin SSOP or 16-pin BCC package.

  • MB15ExxSL Series Single PLL Frequency Synthesizers with On-Chip Prescalers Fact Sheet

    The Fujitsu ExxSL series single PLLs are serial input frequency synthesizers operating up to 2.5 GHz. They have built-in dual-modulus prescalers enabling pulse swallow operation. The latest advanced BiCMOS technology is used resulting in a super low supply current. A refined charge pump design (Fujitsu’s Super Charger) provides fast tuning along with low spurious noise and phase noise characteristics. The E-series is ideally suited for digital mobile communications, including GSM, DCS1800, PCS1900, IS-136, IS-95 and ISM applications.

  • MB15F7xUL Dual PLL Frequency Synthesisers

    The Fujitsu MB15F7xUL series dual PLLs are serial input frequency synthesisers operating up to 6 GHz. They have built-in dual-modulus prescalers enabling pulse swallow operation. The latest advanced BiCMOS technology is used resulting in a super low supply current. A new charge pump design provides fast tuning along with low spurious noise and phase noise characteristics. A new BCC-20 package decreases the mounting area by more than 30% over the previous BCC-16 package

  • MB15F8xUL Fractional-N / Integer Dual PLL Frequency Synthesisers

    The Fujitsu MB15F8xUL series dual PLLs are serial input Fractional-N (SCCT) / Integer frequency synthesisers. Fujitsu’s own approach to reduce the fractional spurious without having impact on the chip size, is called Spurious Cancellation based on standardised Constant Time (SCCT). This results in a small, cost-effective chip that provides fast hopping during lockup and suppresses the spurious after the synthesiser has locked.

  • MB15F8xUL Series Fractional-N / Integer dual PLL Frequency Synthesizers Fact Sheet

    The Fujitsu MB15F8xUL series dual PLLs are serial input Frequency synthesizers. The Fractional-N PLL operates up to 2.6 GHz and the integer PLL operates up to 1200 MHz. They have built-in dual-modulus prescalers enabling pulse swallow operation and fixed or selectable fractional modulo. The latest advanced
    BiCMOS technology is used resulting in a super low supply current. A refined charge pump design (Fujitsu’s Super Charger) provides fast tuning along with low spurious noise and phase noise characteristics. The MB15F8xUL series is ideally suited for digital mobile communications, including GSM, DCS1800, PCS1900, IS-136, IS-95 and ISM applications.

  • MB15FxxSL Series Dual PLL Frequency Synthesizers with On-Chip Prescalers Fact Sheet

    The Fujitsu FxxSL series dual PLLs are serial input frequency synthesizers operating up to 2.5 GHz. They have built-in dual-modulus prescalers enabling pulse swallow operation. The latest advanced BiCMOS technology is used resulting in a super low supply current. A refined charge pump design (Fujitsu’s Super Charger) provides fast tuning along with low spurious noise and phase noise characteristics. The F-series is ideally suited for digital mobile communications, including GSM, DCS1800, PCS1900, IS-136, IS-95: and ISM applications.

  • MB15FxxUL Series Dual PLL Frequency Synthesizers with On-Chip Prescalers Fact Sheet

    The Fujitsu FxxSL series dual PLLs are serial input frequency synthesizers operating up to 6 GHz. They have built-in dual-modulus prescalers enabling pulse swallow operation. The latest advanced BiCMOS technology is used resulting in a
    super low supply current. A new charge pump design provides fast tuning along with low spurious noise and phase noise characteristics. The F-series is ideally suited for digital mobile communications, including GSM, DCS1800, PCS1900, IS-136, IS-95 and ISM applications. A new BCC-20 package decreases the mounting area by more than 30% over the older BCC-16 package.

  • MB15U36 Dual PLL Frequency Synthesizer with On-Chip Prescaler Fact Sheet

    The Fujitsu MB15U36 dual PLL is a serial input frequency synthesizer with 2.0 GHz and 1.2GHz prescalers.The prescalers both have a selectable dual modulus division ratio of 64/65 or 128/129 enabling pulse swallow operation. The MB15U36 utilizes a refined charge pump design (Fujitsu’s Super Charger)that provides fast tuning along with low spurious noise and phase noise characteristics. TheMB15U36
    is ideally suited for digitalmobile communications, including GSM, DCS1800, PCS1900, IS-136, IS-95 and ISM-band applications.

  • MB39A103

    The Fujitsu MB15E03SL is a serial input Phase Locked Loop (PLL) frequency synthesizer with a 1.2 GHz prescaler. The 1.2 GHz prescaler has a dual modulus division ratio of 64/65 or 128/129 enabling pulse swallowing operation.

  • SEMI CUSTOM, IF Band, PLL Frequency Synthesizer, MB15C100 Series Datasheet

    The Fujitsu MB15C100 series is an exclusive Intermediate Frequency (IF) band Phase Locked Loop (PLL) frequency synthesizer with pulse swallow operation. It can operate maximum at 500 MHz.

  • Single Serial Input PLL Frequency Synthesizer On-Chip 1.2 GHz Prescaler MB15E03L Datsheet

    The Fujitsu MB15E03L is serial input Phase Locked Loop (PLL) frequency synthesizer with a 1.2 GHz prescaler. A 64/65 or a 128/129 can be selected for the prescaler that enables pulse swallow operation.

  • Single Serial Input PLL Frequency Synthesizer On-Chip 2.0 GHz Prescaler MB15E05L Datasheet

    The Fujitsu MB15E05L is serial input Phase Locked Loop (PLL) frequency synthesizer with a 2.0 GHz prescaler. A 64/65 or a 128/129 can be selected for the prescaler that enables pulse swallow operation.

  • Single Serial Input PLL Frequency Synthesizer On-chip 2.0 GHz Prescaler MB15E05SL Datasheet

    The Fujitsu MB15E05SL is a serial input Phase Locked Loop (PLL) frequency synthesizer with a 2.0 GHz prescaler. The 2.0 GHz prescaler has a dual modulus division ratio of 64/65 or 128/129 enabling pulse swallowing operation.

  • Single Serial Input PLL Frequency Synthesizer On-Chip 2.5 GHz prescaler
    MB15E07L Datasheet

    The Fujitsu MB15E07L is serial input Phase Locked Loop (PLL) frequency synthesizer with a 2.5 GHz prescaler. A 32/33 or a 64/65 can be selected for the prescaler that enables pulse swallow operation.

  • Single Serial Input PLL Frequency Synthesizer On-chip 2.5 GHz Prescaler MB15E07SL Datasheet

    The Fujitsu MB15E07SL is a serial input Phase Locked Loop (PLL) frequency synthesizer with a 2.5 GHz prescaler. The 2.5 GHz prescaler has a dual modulus division ratio of 32/33 or 64/65 enabling pulse swallowing operation.

  • Single Serial Input PLL Frequency Synthesizer On-chip 2.5 GHz Prescaler MB15E07SL Datasheet

    The Fujitsu MB15E07SL is a serial input Phase Locked Loop (PLL) frequency synthesizer with a 2.5 GHz prescaler. The 2.5 GHz prescaler has a dual modulus division ratio of 32/33 or 64/65 enabling pulse swallowing operation.

  • Single Serial Input PLL Frequency Synthesizer On-chip 2.5 GHz Prescaler
    MB15E07SR Datasheet

    The Fujitsu MB15E07SR is a serial input Phase Locked Loop (PLL) frequency synthesizer with a 2.5 GHz prescaler. The 2.5 GHz prescaler has a dual modulus division ratio of 32/33 or 64/65 enabling pulse swallowing operation.

  • Single Serial Input PLL Frequency Synthesizer On-chip 3.0 GHz Prescaler MB15E06SR Datasheet

    The Fujitsu MB15E06SR is a serial input Phase Locked Loop (PLL) frequency synthesizer with a 3.0 GHz prescaler. The 3.0 GHz prescaler has a dual modulus division ratio of 64/65 or 128/129 enabling pulse swallowing operation.

  • Super PLL Application Guide

    Fujitsu’s Super PLLs are designed to be used in frequency synthesizers for programmable and fixed local oscillator generation in modern radio systems. Applications range from 1V, 100 MHz pagers to 3V operation for Global System for Mobile Communications (GSM), and other cellular and cordless standards. These standards include applications in the second ISM band between 2.4 GHz and 2.483 GHz. Figure 1 shows a simplified representation of a PLL frequency synthesizer. The shaded blocks represent those integrated in a Super PLL Integrated Circuit (IC).

  • Wireless ASSP Part Number Guide

    (PWM method) while achieving support for low voltage startup (1.7V～). Four built-in channels in a TSSOP-30P/BCC-32P package enable control and soft-startup on each channel.

PMIC