Fujitsu Awarded Imperial Invention Prize for High-Dimensional Supercomputer Interconnect Technology

Tokyo, May 29, 2014

Fujitsu today announced that its invention of high-dimensional interconnect technology⁽¹⁾, which is used in the K computer⁽²⁾ Fujitsu jointly developed with RIKEN as well as the company's own FUJITSU Supercomputer PRIMEHPC FX10, was awarded the Imperial Invention Prize. This prize is given to the most outstanding invention at the National Commendation for Invention sponsored by the Japan Institute of Invention and Innovation.

The award ceremony is scheduled to be held on July 8, 2014, at the Hotel Okura Tokyo.

Overview

Today, the world's top supercomputers are massively parallel computers with processors connected to up to tens of thousands of nodes. In massively parallel computers, if there is a failure in any of the compute notes, the failed nodes are isolated and the operation of the system is maintained, but the isolation method affects overall system performance and availability. In conventional node structures, pre-partitioned meshes are connected by switches, and when there is a failure, each partition that includes a failed node will be isolated. However, as a result, nodes that have not failed are also included in the isolated partitions, leading to a decline in system availability.

PRIMEHPC FX10

To overcome this problem, Fujitsu invented high-dimensional interconnect technology that does not employ partitioning switches. This technology enables failed nodes to be circumvented, no decline in the level of parallelism that can be executed, and a high level of system availability to be maintained. This technology is being used in the K computer, which interconnects 88,128 nodes, and which was named the world's top-performing supercomputer in the 37th and 38th editions of the TOP500 List⁽³⁾ of the world's top supercomputers in 2011. In addition to the K computer, this technology is employed in the PRIMEHPC FX10, which is deployed in academic institutions and corporations around the world and is also being used in the successor model of the PRIMEHPC FX10, which is currently under development.

Awardees

• Imperial Invention Prize: Yuichiro Ajima, Senior Architect, Next Generation Technical Computing Unit
• Imperial Invention Prize: Tomohiro Inoue, Manager, Next Generation Technical Computing Unit
• Imperial Invention Prize: Shinya Hiramoto, Next Generation Technical Computing Unit
• Distinguished Service Prize for Employment of Invention: Masami Yamamoto, President and Representative Director

About the High-Dimensional Interconnect Technology

This invention is comprised of a predetermined number of nodes that are grouped together on a grid, with the groups linked together using a torus connection configuration. A torus is a structure in which multiple groups are connected in a ring configuration, with the rings connecting different groups combined in a grid. With this invention, the partitioning of the group can be positioned where one chooses. Since the partitioned units are small, a variety of parallel programs can be simultaneously executed with excellent efficiency. In this configuration, partitioned switches are unnecessary, while the increase in dimensionality has the effect of increasing the number of connection ports, which are all communication paths that contribute to computational performance. In addition, failures can be isolated not only at the level of individual partitions, but within the partitions as well. In the event of isolation within a partition, a virtual loop connection is used for the seamlessly uninterrupted pathway between the rings connecting the groups and the grid structure within individual groups.

Figure 1 depicts an application example of this invention. In this application example, which is called 6-dimensional mesh/torus, the three dimensions of X, Y, and Z depicted in the figure are the rings that connect groups, and the three dimensions of A, B, and C are the grid structures within the groups. In this example, the size of the grid structure within the groups is 2 nodes (A) × 3 nodes (B) × 2 nodes (C). Figure 2 depicts an example of a node failure that has been isolated within a partition. When the size of the grid structure within a group is three or more nodes, even if one node fails within the group, a seamlessly uninterrupted pathway can be maintained that circumvents the failed node.

As a result of this invention, Fujitsu's supercomputers are equipped with highly flexible partitioning functions, enabling a variety of parallel programs to be executed simultaneously.

Figure1. Application example of this technology: 6D mesh/torus

Figure 2. Example of a node failure that has been isolated within a partition

About the National Commendation for Invention

The National Commendation for Invention, which is funded by Imperial Grants received every year from the Imperial Household, is held with the objective of contributing to progress in science and technology and the advancement of industry in Japan by commending individuals for their exceptional achievements, including both the creators of inventions and designs as well as the individuals responsible for fostering and implementing these inventions. The Imperial Invention Prize, which is the top prize, is awarded to the inventors behind the invention that is deemed to be the most outstanding.

For more information

• Innovative "6-Dimensional Mesh/Torus" Topology Network Technology
• Fujitsu Technical Computing