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  7. Fujitsu Releases AccelArray™ Structured ASIC Devices

Fujitsu Releases AccelArray™ Structured ASIC Devices

Accelerates Time-to-Market and Reduces NRE Costs Through Use of Embedded IP Macros and Standardized Layers for Basic System Circuitry

Fujitsu Limited

Tokyo, June 26, 2003

Fujitsu Limited today announced the release of the AccelArray™ structured ASIC devices that deliver faster, less costly development times through the use of standardized interconnect layers for basic system circuitry and key IP macros embedded in the base master of the architecture. AccelArray ASICs are built on Fujitsu's advanced 0.11-micron process to achieve performance on par with standard cell ASICs in 0.11-micron technology.

These AccelArray ASICs target telecommunications and industrial automation applications, in which product cycles are increasingly compressed and delivering high performance at low prices is a market necessity.

The new chip offers an ideal mix of features, combining the flexibility and fast development cycles of field programmable gate arrays (FPGAs) with the compactness and high performance of standard cell ASICs.

Because the key IP macros are already embedded into the base master, operating speed and performance integrity are assured. Of a total of six interconnect layers, three are standardized layers for basic system circuitry, such as clock trees, leaving only the remaining three to be customized in accordance with the customer's specifications. Compared with conventional standard-cell chips(1), the streamlined task of customization offered by AccelArray cuts development times by roughly 50% and non-recurring engineering (NRE) costs by roughly 30%.

Use of the company's FAITH™(2) design consulting service for more efficient chip design ensures a smooth migration from FPGA to the AccelArray platform for volume production. For designs slated for low or medium-scale production volumes, FPGA can be used for sample shipments, and then full-scale production can be implemented in AccelArray at a lower per-chip price immediately after the specification is set, resulting in a faster design and development cycle that makes more efficient use of development resources.

Fujitsu has developed this product especially for telecommunications equipment, to meet its growing demands for shorter product cycles, lower costs and higher performance levels, as well as LSI testers and other industrial automation applications. By delivering high-performance structured ASIC platforms, Fujitsu seeks to expand its position in the high-end FPGA market, building on its strong position in the ASIC field-three years running as Japan's leading ASIC vendor by revenue.

Sample pricing and availability

Price: From 40,000 yen in Japan (see note)

Shipment: late August, 2003

Note: Unit price for very limited samples. Includes no design-development costs.

Main features

1. Embedded IP macros and standardized layers for basic system circuitry for accelerated time-to-market and reduced NRE costs

  1. Standardized layers for basic system circuitry
    Of the six interconnect layers, three are standardized for basic system circuitry, so only the remaining three need to be customized in accordance with customer specifications. To reduce design work, AccelArray ASIC's pre-defined system circuitry has the following features:

    - Includes eight sources of clock signals, with phase-locked loop (PLL) circuit included.
    - To ensure reliable signal propagation, cells and interconnections are laid out to avoid delay variations due to cross-talk noise as well as variations that have been adjusted to the timing calculator.
    - A SCAN circuit and a built-in self test (BIST) circuit are included in the finished component to simplify testing, so overall test circuit and program development time is greatly reduced.
  2. IP macros embedded in base master
    The key IP macros are embedded in the base master, assuring operating speed and functional performance. To give customers more flexibility, base masters are available in five built-in gates (455 kilogates to 3,416 kilogates), each of which has 400Mbps of data I/O. Moreover, Fujitsu is developing a base master capable of handling data I/O at speeds up to 3.125Gbps, as well as a variety of additional IP macros for higher performance.

2. Advanced 0.11-µm process technology

AccelArray ASICs are built on advanced 0.11-micron process technology to give performance on par with conventional standard cell ASICs with 0.11-micron technology.

3. Uses Fujitsu's FAITH design consulting service for smooth migration from FPGA

For designs slated for low or medium-scale production volumes, customers can make prototypes in FPGA and smoothly transition them over to the AccelArray platform for volume production, immediately after finalizing the specification. The AccelArray architecture optimizes per unit costs and turnaround times. Normally, after finalizing a specification at the FPGA stage, customers would need to begin developing the AccelArray design from scratch. But with the FAITH design technique, both FPGA and AccelArray development can take place concurrently for a faster transition to full production.

Main specifications

Power supply: 1.2V ± 0.1V

Number of gates: 455 to 3,416 kilogates

Operating frequency: 333MHz

Packaging: 625-pin to 1681-pin FCBGA

Attachments

AccelArray™ Specifications (16 KB)


  • [1] conventional standard-cell chips

    Refers to Fujitsu's CS91 Series standard-cell design

  • [2] FAITH™

    A design-consulting and design service for concurrent FPGA, PLD, and ASIC development from Fujitsu Kyushu Digital Technologies Limited. Provides consultation in the initial design phase, and keeps FPGA, PLD, and ASIC development in parallel to reduce development times and costs.

About Fujitsu

Fujitsu is a leading provider of customer-focused IT and communications solutions for the global marketplace. Pace-setting technologies, highly reliable computing and telecommunications platforms, and a worldwide corps of systems and services experts uniquely position Fujitsu to deliver comprehensive solutions that open up infinite possibilities for its customers' success. Headquartered in Tokyo, Fujitsu Limited (TSE:6702) reported consolidated revenues of 4.6 trillion yen (US$38 billion) for the fiscal year ended March 31, 2003.  
For more information, please see: www.fujitsu.com

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All company/product names mentioned may be trademarks or registered trademarks of their respective holders and are used for identification purpose only.

Please understand that product prices, specifications and other details are current on the day of issue of the press release, however, may change thereafter without notice.

Date: 26 June, 2003
City: Tokyo
Company: Fujitsu Limited, , , , ,

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