Fujitsu Semiconductor Europe (FSEU) has demonstrated the transmission of >100Gbps over a single CEI-28G-VSR channel, effectively quadrupling the data rate throughput defined by the Optical Internetworking Forum (OIF) for this chip-to-chip electrical interface. This serves as a benchmark for what can be achieved over short-reach electrical channels using the same field-proven CMOS converter technology deployed in long-haul optical transport systems today. Key to the study is a comparison of the relative advantages and disadvantages of PAM (Pulse-amplitude Modulation) encoding versus DMT (Discrete Multi-Tone) over this particular channel. FSEU’s test and demonstration platform is based on the test chips and evaluation boards for the family of 40nm, 65GSps CMOS converters (“LEIA” DAC for transmit and “LUKE” ADC for receive).
The need for faster interconnects and higher port densities within data centres is driving the requirement for higher short-reach transmission rates across boards, through backplanes and between servers. However, there are fundamental challenges in designing short-range interconnects over 30Gbps across even short traces. Here, the limit of efficient signal propagation using standard materials is reached.
Equally, in optical transport networks, increased data traffic is pushing up the speeds required at the core of the network. This is driving the need for higher data rates in metro networks where cost, power and flexibility are key requirements. Over the last few years, the use of coherent detection in long-haul transport links enabled greater performance and flexibility of design by harnessing the capabilities of digital signal processing, enabled by high-speed converters; all built in standard CMOS technologies. As the market moves forward, the expectation is that the same approach will be needed to transport 100Gbps (and higher) data rates over a few 10’s of kilometres of fibre.
In both cases, the use of multi-level signalling or multi-carrier encoding will enable transmission of higher data rates. For short-reach electrical interconnect, the motivation will be to increase the data throughput over the same link. For short-reach metro links, the motivation will be to reduce cost and total system power by maintaining a low signalling frequency (e.g., 10GBaud) and using encoding to transmit more bits/symbol over less expensive optics.
The range of potential application spaces where multi-level signalling may apply is very wide; anything from a few centimetres between chips and modules to several hundred meters across a data centre to a few kilometres. The common theme is that some form of non-binary signalling would allow for a much more scalable and flexible approach and is viable as long as the power/Gbps is low enough.
Fujitsu Research and Development Center and Fujitsu Laboratories will present results of related studies at the upcoming European Conference on Optical Communications (ECOC) in Amsterdam from September 16 to 20. Fujitsu Semiconductor will be showing a live demonstrator to an invited audience and will also be present at the ECOC exhibition hall, booth number 347, where there will be opportunities to discuss the FSEU ADC/DAC technology.
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