Multi-core multi-thread processor SPARC64™ VI
SPARC64 VI enhances the high performance and high reliability features of SPARC64 V and further boosts performance using multi-core and multi-thread per core technology imbedded on a single CPU chip.
The multi-core, multi thread per core, and large on chip cache memory provides a significant boost over single chip performance.
Multi-threading technology minimizes CPU core wait times and increases CPU core utilization.
A large level2 cache memory seriously shrinks memory latency.
SPARC64 V high performance technologies such as super scalar, Out-of-Order execution, branch prediction and non-blocking cache are maintained.
SPARC Enterprise with high-performance SPARC64 VI chips provides supreme performance across a wide range of applications including large-scale transaction processing.
| SPARC64 V | SPARC64 VI | |
|---|---|---|
| CPU cores per chip | 1 | 2 |
| Threads per CPU core | 1 | 2 |
| Level1 cache | 256KB, 2way | 256KB, 2way (per CPU core) |
| Level2 cache | Max 4MB, 4way | Max 6MB, 12way (per CPU chip) |
High Performance Technologies
Multi-core
Single chip performance of SPARC64 VI is much improved by multi-core imbedding in the chip.
Multi-threading
Multi-threading technology minimizes CPU core wait times, increases CPU core utilization.
In single thread per core processors, instruction execution suspends during memory access and resumes after data read action is completed.
Such linear instruction processing takes time.
In multi thread per core processors, when thread1/process 1 starts its memory access, instruction control is switched to thread2 and thread2/process 2 is executed. When thread2 starts its memory access, instruction control is switched back to thread1 and the suspended thread1/process 1 is resumed.
The two thread switching mechanism minimizes processor wait time, efficiently utilizes memory access time and maximizes the performance of SPARC Enterprise mid-range and high-end models.
Other high performance technology
SPARC64 VI incorporates various high performance technologies including: Out of Order Execution: which starts instructions when they have executable data, and Branch Prediction Mechanism: which predicts and prepares for the most likely instruction sequence
SPARC64 VI High performance technology
- Pipeline
- Superscalar
- Out of Order Execution
- Branch Prediction
- Non-blocking cache
- Hardware prefetch
- 16 outstanding instructions
