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FRAM Structure

FRAM(Ferroelectric Random Access Memory) is also known as FeRAM. It is a type of memory that uses a ferroelectric film as a capacitor to store data. This part introduces details of structure of ferroelectric crystal and its reliability.


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What is Ferroelectric?

The figure below explains PZT crystal structure, which is commonly used as a typical ferroelectric material. There are zirconium and titanium in the lattice, which have two stabilization points. They can move between the points according to the external electric field. Once the position is settled, it will not move anymore even the absence of electric filed. Top and bottom electrodes structure a capacitor. Then, the capacitor plots bottom electrode voltage and polarization, which yields a hysteresis loop. Data is stored in the form of "1" or "0".

PZT Crystal Structure and Principles of FRAM

FRAM Cell Crystal structure of PZT(FER) Hysteresis Loop of PZT

  1. Polarization occurs when an electric field is applied. (Zr/Ti ions move upward or downward in the crystal)
  2. Electric polarization remains even in the absence of an applied electric field.
  3. Two stabilized states are stored in the form of "0" or "1" data.

Reliability of FRAM

FRAM is a non-volatile memory device that can hold written data even after it is powered off. Its ability to hold data over long period is called data retention. Data retention is strongly dependent on temperature, so that it is generally provided that the guaranteed retention lifetime (e.g., 10 years) is subject to temperature conditions (e.g., 70°C or less).

The test method for data retention, and the mode of degradation that determines the lifetime of a FRAM are explained below.

(1) Test method

Figure 1. Test flow

Test flow
SS : Same State
OS : Opposite State

As explained above, data retention is strongly dependent on the temperature. Based on this characteristic, it is possible to calculate the long term lifetime of FRAM for a short time period by temperature acceleration. See Figure 1 "Test flow".

A data pattern (e.g., a checkerboard pattern of 0 and 1) is written into the FRAM, and it is left at a high temperature (e.g., 150°C) for a certain time period. Then the data pattern is read out from the FRAM under actual use (e.g., the lowest power supply voltage: 4.5 V, and the highest operational temperature: 85°C), and compared with the original written pattern. Then the reversed data pattern (where 0 and 1 are reversed) is written into the FRAM and the pattern is checked for correctness. Finally, the original data pattern is written into the FRAM again and it is stored at high temperature. This cycle is repeated until there is an error in either the first reading or the second reading. The retention lifetime of a FRAM stored at high temperature is determined.

Of the two readings in the cycle flow, the first reading is called SS (same state) because the original data pattern is read out as it is from a FRAM stored at high temperature and the second reading is called OS (opposite state) because the reversed data pattern is read out from that FRAM.

(2) Dependence on power supply voltage

Figure 2. Graph of QTV characteristic

Graph of QTV characteristic

The writing voltage applied to a ferroelectric capacitor in a memory cell is proportionate to the power supply voltage. On the other hand, the level of polarization of the ferroelectric film is dependent on the applied voltage as shown in Figure 2. The retention tends to be dependent on the level of polarization, so that writing with an insufficient power supply voltage may cause a reduction of retention. The test of data retention as mentioned above is made at the lowest voltage for the guaranteed operation on the catalog (e.g., 4.5 V). Accordingly data retention at a voltage less than that of lowest voltage is not guaranteed.

(3) Mode of degradation

a) Degradation by depolarization

Figure 3. Degradation of the hysteresis characteristic by depolarization

Degradation of the hysteresis characteristic by depolarization

Depolarization means a decrease in the level of polarization of ferroelectric film, which weakens the hysteresis characteristic as shown in Figure 3. Decrease in the level of polarization concerns errors in reading because the FRAM reads data by detecting the levels of polarization.

Depolarization of the FRAM is greater at a higher ambient temperature. When the FRAM is exposed to a temperature, its depolarization is determined in seconds, and stays almost unchanged after that time. Returning the FRAM to the original temperature and rewriting data in it restores the original level of polarization. Failure in retention caused by depolarization means a defect in the SS reading in the evaluation cycle flow as shown in Figure 1.

b) Degradation by imprint

Figure 4. Degradation of the hysteresis characteristic by imprint

Degradation of the hysteresis characteristic by imprint

Imprint means that the FRAM becomes resistive to reversal in polarization according to data that is written in. A FRAM recognizes 0 and 1 by detecting the levels of polarization, and therefore, it is difficult to read/write the reverse data in a FRAM if imprint occurs. Imprint is observed as a rightward or leftward shift of the hysteresis loop as shown in Figure 4.

The OS reading in the evaluation cycle flow in Figure 1 is done to check this mode of degradation.


Figure 5. Mechanism of fatigue

Mechanism of fatigue

Fatigue means a decrease in the level of polarization caused by repeated reversals of polarization of the ferroelectric film See Figure 5.
Fatigue caused by repeated reversals of polarization occurs not only in writing cycles but also in reading cycles, because there is a reversal in the polarization in a cycle process of operation from reading from a FRAM memory cell to rewriting in it because the reading is destructive to data. Accordingly the number of reversals in the polarization of a FRAM is specified as a number of times of possible access to the memory cells, whether they are in read or write cycles.

The test method for evaluation of fatigue and the modes of degradation are explained below.

(1) Test Method

The test method for fatigue is applying fatigue stress to a FRAM by repeating write or read cycles and then checking that it operates correctly. Assuming that the time of an operation cycle is 250 ns for a 64 k bit FRAM in an organization of 8 k words x 8 bits, the test time it takes to apply the fatigue stress to the FRAM is calculated as follows. Eight bits are simultaneously applied with stress at one time of access, so that it takes 8 k (8,192) cycles to apply fatigue to all the memory cells. For example, the times it takes to implement some test times are calculated as follows.

10EXP8 ; 250ns x 8,192  x 10EXP8 = 57 hour (=2.37 days)
10EXP10 ; 250ns x 8,192  x 10EXP10 = 5700 hour (=237 days)
10EXP12 ; 250ns x 8,192  x 10EXP12 = 65 years

As shown above, performing the test of fatigue at some large numbers of cycles is unrealistic. The following methods are taken to substitute for such evaluation.

  1. Acceleration of fatigue by applying an excessive voltage
  2. Limiting the number of cells to be stressed (sampling test)
  3. Applying stress to many devices simultaneously (simultaneous measurement test)

For example, a.) voltage acceleration accelerates by approximately 10 times the fatigue in a FRAM by applying an increment of 1 V to FRAM. The method b.) is generally combined with the method c.) not to under-evaluate fluctuation in the characteristic among cells.

(2) Mode of degradation

The detailed mechanism of degradation by fatigue has not fully been elucidated. It is, however, known that fatigue causes some phenomena that are similar to those caused by depolarization as the mode of retention degradation. It is different from the depolarization in that the FRAM is not restored to the original level of polarization by rewriting.

Data Retention after Fatigue

Figure 6. Retention after fatigue stress (prediction)

Retention after fatigue stress (prediction)

Data retention and fatigue are related to each other in the actual use of a FRAM. The retention characteristic of a memory cell given more fatigue is considered to be generally weaker than that of a memory cell given less fatigue (Figure 6). To study that relationship, data retention is tested on devices using a various number of fatigue stress cycles.

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