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V-by-One HS IP Core

V-by-One HS IP Core logo

The V-by-One®HS standard has been developed by THine Electronics Inc. to offer capabilities for FPD markets that are requiring ever-higher frame rates and higher resolutions.
Tokyo Electron Device (TED) offers the V-by-One®HS IP Core for Xilinx FPGA that achieves reducing the cable pairs, costs and time to market. .


  • Targets a high speed video signal transmittion based on internal connection of the equipment.
  • Up to 3.75Gbps data rate (effective data rate 3Gbps) per lane.
  • Data scrambling and Clock Data Recovery (CDR) to reduce EMI.
  • CDR solves the skew problem between clock and data at conventional transfer system
Resolution Refresh rate (Pixel Clock) Color depth *1 No. of Data Lane
HD 60Hz (74.25MHz) 18/24/30/36 bit 1
120Hz (148.5MHz) 18/24/30/36 bit 2
240Hz (297MHz) 18/24/30/36 bit 4
Full-HD 60Hz (148.5MHz) 18/24/30/36 bit 2
120Hz (297MHz) 18/24/30/36 bit 4
240Hz (594MHz) 18/24/30/36 bit 8
4Kx2K 60Hz (594MHz) 18/24/30/36 bit 8
120Hz (1188MHz) 18/24/30/36 bit 16 *2
240Hz (2376MHz) 18/24/30/36 bit 32 *2

*1) Supported color depth & data lanes by IP Core depend on the target FPGA sevice.
*2) Design service for 16 or 32 lanes is available.

Data SheetOpen a new window
User Manual (transmitting end)Open a new window
User Manual (receiving end)Open a new window


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