DLL: High Density Substrates
Related to the recent performance improvement of electronic devices using Build-up Substrates produced by the Direct Laser & Lamination (DLL®) Process, have seen increases in demand due to achieving the dual benefits of higher-speed and higher-density. SHINKO has achieved these requirements by providing Build-up Substrates that have the outstanding features of fine line patterning through the use of a semi additive process, multi-layer structure, excellent electric characteristics and design flexibility through the use of stacked via structures.
Also IC design and technology has accelerated the use of high-density and high-speed packages. These packages have strong requirements for high-density, good electrical performance and a thinner structure.
Therefore, SHINKO developed the coreless package(DLL3®) which has an unmatched thinner structure coupled with good electrical performance and high design flexibility. This superlative coreless package was achieved by removing the core layer which held back electrical performance and design flexibility.
Also, SHINKO will continue to focus on the development of the next generation packages. These packages will exhibit features that enable even higher-speed, higher-density, more compact and thinner package size required by future markets.
The increase in IC size and the development of advanced chip functions have placed new demands on improving the thermal dissipation and electrical properties of semiconductor packages. To meet these new demands, SHINKO is developing and manufacturing a variety of lead frames, such as stamping lead frames with 256 pins; etching lead frames, suitable for quick delivery requirements; multilayered (advanced) lead frames with superior heat-dissipation properties; and leads on chips (LOC*) for memory purposes. Shinko also develops super fine-pitch, matrix, and deep downset lead frames. SHINKO strives to improve package development and manufacturing from many perspectives. For example, Shinko is promoting the use of a lead-free palladium plating process, which will contribute toward protecting the global environment.
*LOC: A lead frame extended onto the IC and wire-bonded in the center of the chip
One stop for all
All required function for manufacturing Leadframes are joined in Shinko:
- Stamping / Etching
- Downset and Cutting
Stamped Lead Frame - Super Fine Pitch
By placing an inner lead close to IC chip made possible for stabilized production of IC packaging and a significant amount of cost reduction.
Plastic Very Thin Quad Flat Non-leaded Leadframes
Palladium Preplated Leadframe
Higher functional characteristics is achieved by palladium plating in addition to nickel-plating on the lead frame
Solder processing at IC assembly is not required therefore it becomes possible to reduce assembly cost.
Lead, which is potentially damaging to the environment, is not produced.