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Low-power CMOS technology DDC


The power voltage needs to be lowered in order to reduce the power consumption of the CMOS circuit. Previously, power voltage was lowered by reducing transistor size.
However, since the 90 nm process, the variations of threshold voltages resulted from the transistor's dopant fluctuations had been making it difficult for power voltage to be lowered by reduction in transistor size.

The DDC transistor structure is shown in Diagram 1.
For the channel part of the planer CMOS structure, dopant fluctuations can be reduced by creating multiple layers with different impurity concentrations. This resulted in the reduction of power consumption achieved by lower power voltage.

Diagram 1 DDC transistor structure

A DDC transistor (Diagram 1) contains layers of different dopant concentrations at the channel region. This structure helps reduce the fluctuation in the dopant distribution, which is a major cause of the threshold voltage variation, thus enables the lower supply voltage. Since the transistor is built on the conventional planar CMOS structure, it can be manufactured with the conventional semiconductor fabrication equipment. There is also another advantage of having the conventional CMOS structure, that circuit developers can reuse the existing design resources.

Fujitsu Semiconductor has developed CS250S, a combination of the 55nm process in Mie Plant and the DDC, and successfully implemented the DDC technology into production for the first time in the world. In addition to reducing the dopant fluctuation by DDC, Adaptive Body Bias (ABB) control, which compensates the other process-induced variations by applying an optimum body bias for each die, CS250S has achieved the 50% lower active power compared with the conventional technology, while maintaining the same operation speed.

Press Release

Conference Presentation Documents

  • 2013 IEDM
    Embedded FLOTOX Flash on Ultra-Low Power 55nm Logic DDC Platform [Paper (1.08 MB ) / Presentation (1.27 MB )]
  • 2012 IEDM
    A Highly Integrated 65-nm SoC Process with Enhanced Power/Performance of Digital and Analog Circuits [Paper (2.96 MB ) / Presentation (950 KB)]
  • 2011 IEDM
    Advanced Channel Engineering Achieving Aggressive Reduction of VT Variation for Ultra-Low-Power Applications [Paper (613 KB) / Presentation (2.55 MB )]