A dielectric film is deposited as an inter layer dielectric, a trench pattern is formed by photo resist patterning and etching, and trenches are filled with Cu (copper) metal by electroplating.
The method of filling only the trenches with Cu is called single damascene.
Metal-1 Cu filling: A Cu film is deposited in the trenches by electroplating.
Metal-1 Cu Polishing: Excess Cu is removed by surface polishing to leave Cu only in the trenches.
A thick film of silicon oxide or similar material is formed on the silicon wafer surface using the CVD method.
Using the metal-1 trench resist pattern as a mask, trenches are formed in the dielectric film by performing etching treatment. After etching, the resist pattern is removed.
FEOL (Front End of Line: substrate process, the first half of wafer processing)
| 1. Isolation | 2. Well and channel formation | 3. Gate oxidation and gate formation
| 4. LDD formation | 5. Side wall spacers | 6. Source/drain | 7. Silicide | 8. Dielectric film |
9. Contact holes |
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