The interconnect process for connecting elements such as transistors starts from this step.
Dielectric film deposition: A thick silicon oxide film or the like is formed by CVD.
Dielectric film polishing: The silicon oxide film is polished for the film planarization of the wafer surface.
A thick film of silicon oxide or similar material is formed on the silicon wafer surface using the CVD method.
Simply forming a dielectric film results in unevenness of the wafer surface and interferes with subsequent processing.
The oxide film on the surface is polished to make it smooth.
FEOL (Front End of Line: substrate process, the first half of wafer processing)
| 1. Isolation | 2. Well and channel formation | 3. Gate oxidation and gate formation
| 4. LDD formation | 5. Side wall spacers | 6. Source/drain | 7. Silicide | 8. Dielectric film |
9. Contact holes |
Share this page