Abstracts of Magazine FUJITSU 2004-11 (VOL.55, NO.6)

Special Issue : System-on-Chip

• Summary of Fujitsu SoC (System-on-Chip) Technology & Business

It has been about 10 years since the System-on-Chip (SoC) appeared in LSI markets. Continuous advances in process technology and design methodology for SoCs have been made during that time. Because of the increasing complexity of SoCs, the relationship between a semiconductor vendor and its customers has changed from that of a simple "sell & buy" relationship to that of a more complex mutual dependency. This paper describes the recent general trends of SoC technology and business together with Fujitsu's response to these trends. It also describes how Fujitsu plans to handle SoC and LSI business in the future.

• Low-Power MPEG-4 Video CODEC Core

Fujitsu has developed a low-power, high-quality MPEG-4 video CODEC core that can encode video signals at 30 VGA frames per second (fps). To achieve the target performance, a scene adaptive, fast-motion estimation algorithm was applied for a drastic reduction of computing operation, and a post-filter circuit was incorporated in the macroblock processing pipeline to reduce the access to data in external memory. This MPEG-4 video CODEC core has already been used in various System-on-Chips for mobile multimedia devices, including cellular phones and digital cameras. The measured power consumption of the CODEC core is 73 mW during video encoding at 30 VGA fps. This paper describes the power consumption reduction technology used in the MPEG-4 video CODEC core.

• Mobile Multimedia Platform (MMP)

Cellular phones incorporating camera modules are rapidly spreading not only in Japan, but also throughout the world's markets. This growth has led to stronger demands for cellular phones with additional functions and higher quality graphics and pictures. To fully meet these demands, Fujitsu has constructed a Mobile Multimedia Platform (MMP) based on an ARM processor with common IPs. Using this platform, Fujitsu has developed the MB86V00 and MB86V01 as the first LSI products for the cellular phone market. These products provide all of the high-resolution camera/video functions required for cellular phones in a single chip with a low power consumption. This paper describes the concept of the MMP, the development of the LSI products, and the low-power consumption technology used in the LSIs.

• FR-V Family Processors for Media Solutions

This paper introduces the FR-V Family, which consists of VLIW-embedded processors for handling media processing and a companion chip. This Family incorporates the features of a general-purpose processor capable of handling Linux and μITRON and the features of a special-purpose processor capable of handling high-performance media processing. Among the processors of the FR-V Family, this paper describes the 8-way VLIW FR555 processor for high-performance needs, the 2-way VLIW FR400 series for cost-performance needs, and the FR461 for handling standard Linux. The FR461 has a built-in MMU (Memory Management Unit), incorporates the latest System-on-Chip, and can operate at a clock frequency of 400 MHz thanks to the use of advanced design techniques. Moreover, an exclusive media instruction set enables the FR461 to decode MPEG-4 VGA at 30 fps using software. The description of the FR461 includes its physical design methodology, its power-saving mechanism, and the FR461 development kit (VDK).

• Ultra-High-Speed CMOS Interface Technology

Enhancing the performance of the broadband Internet and the performance of computer and storage systems requires high-bandwidth networks to interconnect these systems. Fujitsu has already marketed high-speed network interface products such as the 10 G Ethernet and has recently developed a CMOS interface that accommodates high-speed data transfer at 6.4 Gbps per signal line to increase network bandwidth. For this interface, we have developed a multi-tap pre-emphasis function for the transmitter and an adaptive equalizer for the receiver, which can compensate for a high-frequency transmission loss of 20 dB or more in the backplane of devices and in cables that interconnect cabinets. When this CMOS interface is mounted on a System-on-Chip as a multi-channel interface, the system bandwidth can be upgraded significantly. This paper describes an ultra-high-speed CMOS interface that was manufactured experimentally using a 0.11 μm CMOS process.

• Single-Chip 10-Gigabit Ethernet Switch LSI

Compact, low-cost, and low-latency 10-gigabit Ethernet switches have been urgently needed to connect high-speed servers and large storage systems for constructing flexible, highly reliable IT systems. To meet this need, Fujitsu has developed the world's first single-chip, 10-gigabit Ethernet switch LSI, which features 12 ports for the 10-gigabit Ethernet interface and layer-2 switch functions. This LSI has a newly developed I-O circuit (eXAUI) that can transfer 10-gigabit Ethernet signals over a 25-meter copper cable, thus making it possible to reduce the size, cost, and power consumption of IT systems. We have already developed 10-gigabit Ethernet switches incorporating this LSI, and they are now in use in data centers and high-performance computers. This paper describes the key technologies applied to this LSI, its functions and structure, the structure of the eXAUI circuit, and the integration of its circuits. This paper also includes an evaluation of the LSI's performance and a reference board design.

• High-Speed IP/IPsec Processing Engine LSIs

In recent years, we have seen an increase in the speed of Internet access lines together with demands for concealed communications. To meet these demands, we have developed two LSIs, MB86977 and MB86978, which are optimized for use in gateways, such as broadband VPN routers for secure and high-speed communications. The MB86977 is a high-performance IP packet processing engine. After it has been programmed with the appropriate parameters, this device can process bi-directional routing, NAPT, PPPoE, and filtering at 100 Mbps full wire speed. The MB86978 is an IPsec accelerator LSI capable of processing packets inline on the transmission path. Once this device has been programmed, it can perform bi-directional IPsec processing at 100 Mbps full wire speed. This paper describes the functions, performance, and mechanisms of these two LSIs. Then, it describes how these LSIs are superior to software processing solutions. Lastly, this paper introduces reference boards that can facilitate rapid development of broadband VPN routers.

• System-on-Chip with Security Module for Network Home Electronic Appliances

Linking home electronic appliances to the Internet and other networks enables easy access to a variety of information and services. However, this also increases a user's exposure to information leaks, external intrusions, and other risks. Therefore, home electronic appliances linked to the network require proper security functions. This paper describes a single-chip System-on-Chip specifically designed to protect home electronic appliances that are connected to the network. When used as the main processor of a home system, this LSI can provide networking and security functions, control devices, and process the relevant data of those devices. Moreover, this LSI can be connected as a slave processor to an existing system for easy realization of networking and security functions. This paper also describes the optimum CPU for home electronic appliances and the various peripheral functions these appliances should have.

• Digital Content Rights Protection LSI for PC-Based Digital TV Receivers

This paper describes a Digital Content Rights Protection LSI that prevents unauthorized reception of digital broadcasts using PCs. Because PC software is basically open (i.e., its software specifications are public knowledge), skilled hackers may gain unauthorized access to the software. As a result, broadcasters and other content holders have concern about potential risks of digital broadcasting softwares, which have stalled the development of PC-software based digital TV receivers for some time. We have therefore designed a content protection scheme that protects content even in open architecture environments such as PCs and implemented it in the Digital Content Rights Protection LSI. This LSI will open the way for authorized persons to watch digital TV broadcasts on their PCs without having to buy a costly digital TV receiver.

• New Structured ASIC: AccelArray

AccelArray is a high-performance, cost-effective, and short time-to-market ASIC manufactured using Fujitsu's 0.11-micron CMOS process technology. It consists of a predefined section that includes global clock trees, DFT test nets, a power-mesh, and layers of customizable wiring. To realize the AccelArray design concept, various essential technologies have been introduced for reducing the design load and risks for the customer. As a result, AccelArray provides a one-third reduction in design turnaround time compared to standard-cell ASICs for large-scale, high-speed System-on-Chips and a significant reduction in total development cost. This paper describes the design concepts of AccelArray and the essential technologies required to realize them. It also describes AccelArray's development environment and layout CAD.

• Coverage-Driven IP Macro Interface Verification Method

LSI design has become a larger and more complex task in recent years. As a result, an IP-based design approach has been attracting attention as a way to accelerate design work. In this approach, existing design circuit modules (IP macros) are reused to increase design efficiency. However, ambiguous specifications and insufficient verifications prevent the design efficiency from being increased as much as expected. In particular, errors caused by interface mismatch are considered to be a serious problem because they cannot be prevented simply by modifying the firmware or restricting IP usage. To solve this problem, we have developed a new verification method that resolves verification insufficiencies due to ambiguities in the IP macro's interface specifications. The verification method features the following: 1) clarification of the interface specifications by describing them in a formal interface specification language called Component Wrapper Language (CWL); 2) automatic, exhaustive extraction of information for the verification process such as the verification properties and degree of verification; and 3) linkage with formal verification techniques and coverage measurement techniques to achieve a highly comprehensive level of verification. This paper introduces the new verification method.

• CAD Tools for Early Timing Closure of System-on-Chip Designs

Due to current design trends such as low-power design and IP reuse, the timing constraints of System-on-Chips are becoming tighter and more complicated. Therefore, early timing closure is becoming more and more difficult in modern System-on-Chip design. In this paper, we introduce two new CAD tools to solve this problem. One is a clock tree synthesis tool called March, and the other is a multi-cycle path analysis tool called MagusMCP. The clock tree synthesis tool, March, provides a framework for generating more flexible clock circuit configurations that make it easier to meet the timing constraints. The multi-cycle path analysis tool, MagusMCP, automatically detects multi-cycle paths based on an analysis that takes the logic of a circuit into account. This has the effect of loosening the timing constraints, which enables early timing closure.

• LSI Noise Model for Power Integrity Analysis

Together with semiconductor technology scaling, power integrity inside System-on-Chips has become a major design issue. To investigate this issue, we created an LSI noise model and developed a simulation methodology to analyze power integrity. Using this methodology, we can simulate noise waveforms inside an LSI to obtain, for example, the simultaneous switching noise of I/O circuits and core noise caused by dynamic LSI currents. We can also use this model in the initial design stage to optimize the power wiring, minimize the power pin count, and thereby minimize System-on-Chip costs. In this paper, we describe the noise that must be taken into consideration when designing an LSI's power system. We then describe the overall configuration and generation flow of the LSI noise model, measurement results of the test chip we used for verifying the model's accuracy, and the application of the model in product development.