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Abstracts of Magazine FUJITSU 2004-5 (VOL.55, NO.3)
Special Issue 1: CS100
- Overview of Fujitsu's New 90 nm CMOS Technologies
Huge volumes of digital data are constantly being exchanged in today's network-oriented society. To keep up with demands, servers are becoming more powerful and mobile communication terminals are becoming smaller. Consequently, LSIs, which are the core components of these devices, need to be more compact and have a higher performance and lower power consumption. In response, Fujitsu has developed two new series of 90 nm CMOS LSIs: the CS100 and the CS100A. The CS100 series makes full use of cutting-edge semiconductor technologies and attains the world's top level of performance. This series is intended for use in servers and other high-end equipment. The CS100A series uses some of the new technologies developed for the CS100 series and provides cost-effective performance. This series is intended to cover the extensive consumer markets for low power consumption mobile devices and digital multimedia equipment (which must process vast amounts of image data at high speed). This paper gives an overview of the CS100 and CS100A series.
- 90 nm CMOS Ultrafast/Low-Leakage Device Technology
This paper describes the transistors of Fujitsu's 90 nm CMOS: CS100 for high-end processors and CS100A for versatile, low-power/high-performance devices such as cellular phones. CS100 transistors were required to drive high current with small parasitic capacitance. Current was increased by reducing gate dielectric thickness to the leakage limit and employing original techniques to improve mobility. Gate capacitance was reduced by shortening the gate length to 40 nm (the world's shortest in the 90 nm node). This was achieved by improving the short channel effect using proprietary techniques for shallow and steep junction. CS100A transistors are designed to offer the best balance between leakage restriction and performance. Both gate and junction leakage specifications were met by adopting the optimal oxide thickness and impurity profile, respectively; while techniques employed to improve mobility for the CS100 boosted performance.
- Cu Interconnection Technology for 90 nm CMOS Devices
This paper describes the copper (Cu) interconnection technologies for 90 nm CMOS devices Fujitsu has developed for cutting-edge information equipment. We have developed and introduced various advanced technologies for element interconnections in 90 nm CMOS devices to meet the requirements for high performance, low power consumption, and compactness. The Cu wiring technology that Fujitsu already introduced early on for 180 nm CMOS devices was fully applied to 90 nm CMOS devices to prevent increased circuit delays due to higher interconnection resistances. Circuit patterns are formed using an ArF laser and optical proximity correction (OPC). The minimum line width is 140 nm, which is 30 percent thinner than in the preceding CMOS generation. An insulating film with a low dielectric constant is used between the interconnections and also between via layers to avoid increases in capacitance between interconnections due to the reduced wire spacing. Furthermore, the introduction of advanced chemical mechanical polishing (CMP) technology enables us to maintain the flatness of wiring layers even when they are laminated and achieve a practical structure of 11 layers (10 Cu and one Al), which is three more layers than in the preceding CMOS generation.
- Construction of 90 nm CMOS Development and Production Line
In 2001, Fujitsu built a new wafer process line in the Akiruno Technology Center in order to develop and commercially produce the world's first 90 nm-node logic devices. To accommodate operations ranging from technological development to commercial production of these devices, several new systems were incorporated into this process line to enhance key factors such as the process speed and flexibility. A standard mechanical interface (SMIF) system was adopted throughout the entire line to support flexible reduction of the startup time and equipment exchange. A computer-integrated manufacturing (CIM) system that had already been time-proven in conventional factories was newly modified and installed to increase the efficiency of technological development. For the new process technologies, an advanced process control (APC) system was introduced to enable highly accurate formation of gates, the "Base Load" product lot was introduced as the indicator for yield improvement, and operation of a new, high-speed fault analysis system was started. This paper outlines the features of the new process line in the Akiruno Technology Center.
- 90 nm CMOS System LSI: CS101 Series
Fujitsu's CS101 series of 90 nm CMOS system LSIs for high-end consumer applications features advanced technologies such as 10-layer copper interconnections and Low-k dielectrics. This series is suitable for a wide range of applications, for example, low power consumption mobile devices; compact, high-functionality consumer digital devices; and high-efficiency network equipment. This series uses the low power consumption technology of Fujitsu's CS100A 90 mm CMOS technology. The leakage current per CS101-series gate has been reduced to 25 pA, which is one-tenth that of conventional products. The power consumption per gate has been reduced to 2.7 nW, which is half that of conventional products and sets a new industry-leading level. The integration has been increased to enable mounting of up to 100 million gates, which is double the maximum number of gates in conventional products. Also, the performance has been improved to enable operation at up to 1.2 GHz, which is more than 25% above the upper limit of conventional products. This paper gives an overview of the CS101 series.
- Reference Design Flow for 90 nm CMOS ASICs
Increasing the level of integration in LSIs basically means increasing the number of gates they contain. Nowadays, application-specific integrated circuits (ASICs) with over 10 million gates are common. The recently developed CS101 series of LSIs can have as many as 100 million gates, which is about double the number of gates in the CS91 series. However, theses improvements in integration have brought new problems. These include a prolonged development period due to the increased number of gates and various problems concerning microfabrication and the new materials used for fabricating cutting-edge LSIs. We have thoroughly reviewed the LSI design environment, focusing on the design of 90 nm LSI layouts. This paper describes the features and effects of the resulting "reference design flow" we constructed for a new design environment.
Special Issue 2: VPS and Physical Simulation
- Development of VPS and Physical Simulation Technologies
Frontloading development is a development method in which different kinds of verifications are performed at an early stage. This method makes it easier to meet some increasingly important requirements in information technology (IT) products, for example, low-cost, high performance, compactness, light weight, and environmental friendliness. An indispensable part of frontloading development is simulation using virtual productions. In this paper, we describe our recent efforts to develop the virtual product simulator (VPS) and physical simulations for product development.
- VPS Plays Central Role in Cooperative Development of Products
Product development has become a very complex and difficult process. Many sections that work with each other have been optimizing their product-development efficiency using 3D-CAD and its data. In the design stage, various verifications must be done for each stage of product development. These verifications and other development tasks can be done more efficiently by making more practical use of 3D models. However, 3D-CAD is very complicated and requires considerable expertise. The Virtual Product Simulator (VPS) makes it possible to handle 3D data through simple operations. It also supports cooperative development by enabling workers to share 3D-designed models. In this paper, we outline VPS and give some examples of its application.
- High-Speed Modeling of VPS/Simulation-HUB
When thermal fluid analysis is applied to the design of electronic equipment, two important issues are how to shorten the modeling time and attain highly accurate analysis results. VPS/Simulation-Hub is a system that resolves these issues by constructing a highly accurate analysis model at high speed. The system has three main features: 1) a robust CAD interface that can batch-convert detailed 3D CAD data from various CAD systems to a highly accurate analysis model, 2) a feature that deletes components not essential to analysis, and 3) a feature that simplifies the shape of the structure being analyzed to improve analytical accuracy. This system was used for thermal fluid analysis of a magneto-optic disk, and it reduced the modeling work-hours to one-seventh and the analytical work-hours to one-third, compared to the work-hours the analysis would have taken previously. This paper introduces VPS/Simulation-Hub.
- Development of General-Purpose Micro-Magnetization Analysis Simulator
The techniques based on the concept of micro-magnetization are used for magnetic simulation in the design of recording heads for hard disks. Micro-magnetization refers to the magnetization of very small magnetic elements. Micro-magnetization simulation is a technique for 1) analyzing the behavior of dynamically changing magnetic structures such as magnetic walls and domains and 2) analyzing stable magnetization states by bringing the energy of magnetic substances divided by micro-magnetization close to a stable state. Because the surface recording density has increased and head microfabrication has progressed, accurate identification of the detailed mechanisms of magnetic fields is required to ensure stable head characteristics. Also, the need for numerical simulations that take the 3-dimensional shape of heads into consideration has increased. We have developed a general-purpose micro-magnetization simulator that uses the finite-volume method for the equations of micro-magnetization movement and the finite-element method for the equations of magnetic fields. This paper gives an overview of this simulator and introduces some examples of how this simulator is being applied to products.
- Application of Simulation to Progressive Pressing
Progressive pressing enables high-speed manufacturing of large amounts of highly accurate parts and is widely used in the manufacture of precision sheet-metal parts. However, the molds used in this process take considerable experience to design, and some mold shapes take a lot of time to prototype. We therefore applied plastic processing analysis to various in-house products, and as a result we can now evaluate a shape's formability and rupture potential without depending on experience and intuition. This paper describes the model we used for plastic processing analysis and its calculation method, the determination of friction coefficients, the verification of accuracy, and the evaluation of formability. This paper also describes our method for evaluating rupture potential using an example of applying plastic processing analysis to the precision sheet-metal parts of a magnetic disk drive.
- Method of Shock Analysis for PCBs Subjected to Ball Impacts
The LSI packages of mobile devices are mainly BGA (Ball Grid Array) packages, which are soldered onto PCBs using minute solder balls. Obviously, the solder joints of these packages must be strong so the device can withstand being dropped, and this is usually checked by conducting drop tests. However, because it is difficult to reproduce the same device orientation and kinetics at the time of impact in each test, the results are not very consistent. To improve the results, we examined a testing method in which the device under test is subjected to the same forces as in a free fall by striking it with a falling steel ball. Then, we developed a device that tests resistance to repeated impacts by a falling steel ball and evaluated its performance. Also, we analyzed the strains and distortions that occur on PCB surfaces during free-fall impacts and impacts by falling steel ball and then compared the analysis results with measurements made in experiments with actual devices. This paper describes the method of shock analysis we used in this investigation.
- Power Integrity Analysis of High-Speed PCBs
With the continuing increase in equipment speed, bounce noise in power and ground planes has recently become a problem and it is now increasingly necessary to analyze this noise. In response, we have developed a power integrity analysis system for analyzing and displaying the power and ground impedances of a printed circuit board (PCB). By using this system, SIGAL-PI, bypass-capacitors, and power and ground planes can be optimized to eliminate bounce noise and also achieve a reduction in the number of components. Moreover, it can cooperate with a floor planner, and since it eliminates noise problems in the specification stage, there is no need to make noise-reducing adjustments in the design stage. As a result, this system greatly reduces the time needed for the design stage. This paper outlines SIGAL-PI and describes an application example and our future plans for the system.
- Electron Device Applications of Carbon Nanotubes
