Abstracts of Magazine FUJITSU 2002-1 (VOL.53, NO.1)

Special Issue : System-on-a-Chip

• Prospects for the System LSI Market

The remarkable reductions that have been achieved in size, price, and power consumption have placed even large, complicated systems within the reach of ordinary individuals. Modern technology can now place an entire, complex system on a single, highly integrated system LSI chip, and the demand for these chips continues to grow as systems become more and more complex and diversified. System LSIs are essential for system differentiation and early market introduction of new products. However, there are several important problems that remain to be solved, for example, we need a design technology that enables highly integrated system LSIs to be developed in a short period. In this paper, we give an overview of system LSI technology and system LSI market trends. We also introduce Fujitsu’s system LSI solutions.

• Total Software Environment for System LSI Development

To meet the demand for faster media processing on today’s diverse, networked systems, an environment for quickly designing high-quality hardware, software and system LSIs is needed. In particular, when developing embedded software containing millions of steps for system LSIs, the quality of the development environment has a significant effect on the product. This report describes the linkage between the high-level CASE tools based on the UML language that will be essential for the future development of embedded software and Softune, which is a conventional development environment. It also describes the compiler technology required for software platform development, embedded Java technology, and middleware libraries capable of supporting the rapidly increasing media and profiles.

• Layout CAD System for System LSI Design

Deep sub-micron process technologies of 0.18μ;m and below enable the integration of logical circuits having more than 10 million gates. Now, we have reached the era of System-on-a-Chip (SOC), which integrates into a single chip a system that up to now has required multiple chips. However, the design terms of SOC have increased because the problems connected with the timing-closure and signal-integrity have become more complicated. To solve these problems and enable system LSI to be designed efficiently within a short term, several new CAD technologies are needed. This paper introduces some CAD technologies, focusing on layout design. These CAD technologies, developed based on 0.25μm technology and enhanced by linkage with the analytic method, have enabled a timing-driven layout, handling of cross-talk errors, and optimization of power supply wires. In addition, these CAD technologies are being employed by the layout CAD system “GLOSCAD”, which is widely used in Fujitsu.

• Lithography CAD Technique for 100 nm-node System LSI

In lithography CAD for photo-exposure, the development of the OPC system using parallel processing has enabled high-speed mask pattern generation and resolution enhancement processing, both of which are becoming more and more difficult for 100 nm-node system LSIs. Also, lithographic DRC, which is used to verify resolution enhancement processing, has helped reduce the development time and prototyping cost of system LSIs. In lithographic CAD for electron-beam exposure, the common block method has been developed as a means of reducing reticle cost, which is an important problem when multiple products are manufactured in varied quantities. A data processing system has been developed to use the partial block extraction function and block extraction simulator for automatic extraction of optimum common block patterns. The electron beam exposure technology not only contributes to developments in advanced technology but also strongly promotes the downward expansion of electron-beam direct writing in terms of both technology and throughput. This paper gives an overview of these techniques for 100 nm-node system LSIs.

• Verification Technology for a Complex System-on-a-Chip

The developers of a complex System-on-a-Chip (SOC) are often unaware of fatal specification problems until the final stages of overall system verification. This prolongs the SOC development period and significantly increases the development cost. Therefore, to develop an SOC efficiently in a short time, it is necessary to verify the system hardware/software design at the early development stage. We have developed a virtual system-prototyping technology based on a C-language modeling approach to enable concurrent hardware/software development from an early stage. We have also developed a rapid prototyping technology based on emulation to rapidly verify an entire system. Fujitsu has used both of these verification technologies to develop various SOCs. We can combine these technologies and determine the optimal sequence of the verification flow according to the SOC to be developed. Our verification methodology enables us to shorten the development period for an SOC and reduce a project’s risk.

• 0.11μm CMOS Technology

This paper introduces a newly developed 0.11μm node CMOS technology suitable for the system LSIs that are needed to realize a comfortable broadband Internet society. For high-speed, low-power consumption devices, a minimum gate length of 0.11μm was developed by combining 0.13μm DUV lithography technology with advanced etching technology. By improving the highly reliable Cu wiring technology developed for LSIs for internal high-end servers of the previous generation, we developed a new ASIC wiring structure made of Cu wires and insulation layers with a low dielectric constant. Because the cross section shape of the Cu wires was optimized, their RC delay times are about 1.6 times shorter than those of aluminum wires and the cross talk noise between adjacent wires, which is regarded as a serious problems, has been remarkably reduced. Recently, the capacity of the internal memory of system LSIs has rapidly increased. We developed large-scale, 8 Mbit internal SRAM chips by using the new circuit technology and reducing the memory cell area by about 50%. This paper gives an overview of the new 0.11 μm technology.

• Design Methodology for Low-Power-Consumption RAM IP

The RAM macros installed in system LSIs now have complicated logical functions and circuits to reduce power consumption and provide high functionality. Furthermore, the LSI design flow for combining these RAM macros with ASICs has become very complicated because the design techniques for hardware IP (e.g., RAM) and ASICs are quite different from each other. To simplify the design flow, we have developed a RAM design methodology that consists of the following steps:
1. A flow for the logical function equivalence check of logical models using actual circuits
2. A delay library generation flow developed by considering process deviation effects and interconnect crosstalk delay
3. A power supply wiring design rule and power-drop verification flow
By using this design methodology, we can minimize differences between the designed library operation and the actual circuit operation. It also enables us to include RAM design (i.e., hardware IP design) into an ASIC design flow with a short turnaround time and solve the RAM macro noise margin problems. This paper describes this methodology.

• Ultra-High-Speed CMOS Interface

This paper introduces an ultra-high-speed CMOS interface that can transmit data at speeds faster than 2.5 Gbps and execute clock recovery from data. It is used for interfacing between LSIs and optical modules, between LSIs on PC board, and between boards via a backplane. This interface can handle high data rates using only CMOS circuits. No special process options are required. The interface also features a low power consumption of approximately 150 mW per channel. Compared with interfaces that use compound semiconductors or SiGe devices, this CMOS interface has a significantly lower power consumption. In addition, multiple channels can be used on a single chip. Moreover, the CMOS interface can also be used as an ASIC macro, which enables multiple channels to be integrated onto a single chip and a reduction in power consumption, package and board costs, and the number of signals. As a result, highperformance, low-cost systems can be configured. Another development is now in progress to achieve source clock synchronization and data rates faster than 10 Gbps.

• New Media-processor "FR400"

We have developed a new media processor, the FR400, which is a member of the high-performance embedded VLIW processor FR-V family. Compared with the FR500, the instruction issue count, number of registers, and cache size of the FR400 have been reduced by half, resulting in lower costs. Nevertheless, by improving performance in all possible ways, cost-performance has been raised significantly. This paper first discusses the concept of VLIW and then describes the instruction set architecture of the FR400. The internal configuration and power-saving feature of the MB93401, which is the first product containing the FR400, are outlined. Finally, the paper discusses the superiority of using the FR400 as the core system LSI for products where image processing algorithms are executed using software, with reference to multi-function printers (MFPs) and digital still cameras (DSCs) as examples.

• Single-chip OFDM Demodulator for Japanese Digital Terrestrial Broadcasting

In Japan, digital terrestrial television broadcasting which can accommodate a variety of broadcasting services will be launched in the year 2003. The Japanese standard is characterized by the use of OFDM (Orthogonal Frequency Division Multiplexing) in the modulation scheme, which provides stable reception in multipath environments. Other features of the Japanese standard are three modes with different carrier spacing, time interleaving for reducing data errors in mobile reception, and hierarchical transmission that enables different programs to be transmitted simultaneously. The demodulator needs a large logic and memory space to provide these functions. To enable broadcasts to be received with various terminals, the demodulator should be built into a single-chip LSI. We designed a new architecture of OFDM demodulation for reducing the on-chip memory space, and succeeded in developing a single-chip LSI. We report on the first single-chip OFDM demodulator for Japanese digital terrestrial television broadcasting.

• CMOS Color Sensor Module for Micro Cameras

CMOS color image sensors are increasingly being used in small digital cameras, cameras for notebook PCs, and personal digital assistants (PDAs), allowing captured images to be sent over the Internet and displayed on cellular phones. As the applications become more diverse, there is a growing demand for smaller, lower power-consumption CMOS color image sensors, to provide greater flexibility of design of cellular phones. This paper introduces the high-resolution, multifunctional CMOS color image sensor module (MB86S02) for micro cameras.

• Single-chip MPEG-2 Audio/Video Encoder LSI

With the advent of rewritable media, inexpensive digital AV equipment that can record compressed images using the MPEG-2 system will likely be developed. We have therefore developed an encoder LSI that integrates both video and audio MPEG-2 encoding on a single chip. This LSI enables the cost of MPEG-2 recording systems to be reduced. The LSI also offers low power consumption, flexibility, and high picture quality through the use of a mixed hardware/software architecture. A codec module prototype has been developed using this LSI, and future application systems can also be easily built using this module. As an example, we have built a hard disk recording system and confirmed that recording and playback can be executed simultaneously.

• Story of DSC System LSI

We have just developed the Millennia series of system LSIs for digital still cameras (DSCs). These LSIs are 1-chip devices that contain an FR70E CPU core, high-speed and high-quality picture processing macros, and interfaces for peripheral devices such as memory cards. This chip enables even customers with little skill in DSC design to develop original products easily. This paperdescribes the system configuration, chip organization, and road map of the Millennia series.

• High-Performance Graphics Controller

This paper introduces the MB86290 series of high-performance graphics controller LSIs. This series is ideal for various types of embedded applications, for example, car navigation, digital panel meters, and display panels. The third-generation product of this series, the MB86293, contains a 2D/3D rendering engine, geometry processor, display controller, video capture unit, external memory controller, and host interface controller. This LSI now makes it possible to embed the graphics capabilities found in PCs and home game machines, for example, high-quality, high-performance 2D graphics rendering and multi-layered display. This paper mainly describes some actual applications of an advanced display controller and rendering engine that is based on this LSI. It also presents a performance comparison that shows the advantages of using this LSI in embedded applications.

• Fishery Resource Conservation: fresco

A Fishery Resource Conservation (fresco) system has been designed for examining resources, forecast trends, and develop the best management techniques for the preservation and reasonable use of fishery resources. The system has been designed for use in the Fishery Resource Conservation program of the Fisheries Agency. A fresco server has been installed in the Japan Fisheries Information Service Center (JAFIC) to collect fishing and oceanic information from 10 Fishery Research Laboratories and 54 Fisheries Experiment Stations located throughout the country. The fresco server manages this information using a database. The JAFIC entrusted Fujitsu with the development of this system, and Fujitsu completed it in 2000. This paper provides a summary of this fresco and describes its configuration, focusing on the relatively difficult functions required by the customer.