Abstracts of Magazine FUJITSU 1999-11 (VOL.50, NO.6)

Special Issue : Fujitsu's CAD Systems

• Design and Verification System for Specification Levels: Supervise

Hardware systems continue to grow in scale and complexity, and there is a strong demand for even shorter development periods. To meet this requirement, Fujitsu and ICL have developed a design and verification system for specification levels called “Supervise,” and have realized a seamless design and verification environment by providing integrated support for the development stages from specification to detail design. Supervise uses VHDL+, which is an extended hardware design language of VHDL that enables abstract descriptions of data and timing and thus enables simulation at the early stages of specification design. We expect that Supervise can reduce the verification period by 20 to 30％.
This paper first describes the key functions of Supervise and points out its wide range of applications, which include system design, IP reuse, test bench generation, and protocol verification. Then, several examples of applying Supervise to the design of devices for Fujitsu networks are introduced. Finally, the future prospects of the system, including efforts that have been taken for IEEE standardization, synthesis at higher levels, and co-design of hardware and software, are described.

• Logic Equivalence Verification System: ASSURE

This paper introduces a logic equivalence verification system called “ASSURE” developed by Fujitsu Laboratories of America （FLA） for verifying logic equivalence in two circuits. ASSURE combines multiple verification algorithms with its unique heuristic method to realize faster and more successful verification than other tools in the market. This verification tool can therefore even be applied to designs as large as several million gates.
ASSURE has practical functions based on the latest verification technologies developed by FLA, for example, automatic flip-flop matching and diagnosis for design errors. It also provides a superior environment for design verification that guarantees 100％ verification coverage by supplementing the conventional logic simulation used for design verification, which has been causing problems such as increasing verification times and decreasing coverage rates.

• Case Study of Applying Symbolic Model Checking System: BINGO

Simulation has been widely used for logic verification of LSI. However, because of the increasing complexity of these devices it is now considered difficult to verify them within a reasonable number of person-hours and at an acceptably high level of coverage.
On the other hand, symbolic model checking is now becoming practical due to progress that has been achieved in formal verification technologies. This technology guarantees 100％ coverage for specified verification properties, but restricts the manageable scale of the device. Therefore, symbolic model checking technology should be used as a supplement to verify the parts which a simulation has failed to cover, rather than for verifying an entire LSI.
This paper introduces the work being done by Fujitsu Laboratories Ltd. on symbolic model checking. It then describes a case study of a symbolic model checking system developed by the authors called “BINGO.” In this study, several techniques for the effective application of symbolic model checking to large designs were used.

• Technologies of Performance-driven Logic Synthesis

This paper describes two logic synthesis technologies used to reduce delay in large-scale circuits. In the repetitive local delay improvement generally done for large-scale circuits, it is important to know where and how to change a circuit.
The first half of this paper describes technology mapping for solving the problem of “how.” Particularly, a method of obtaining an optimal combination of library cells given by a tree-covering algorithm is introduced. This method allows automatic generation of a circuit that has the required delay and area characteristics. The second half of this paper introduces a technology developed by Fujitsu for solving the problem of “where.” This technology uses “separator sets” to optimally specify locations where delay needs to be improved. Experiments have shown that a combination of these two technologies can reliably improve delays in large-scale circuits.

• Timing-driven Placement System: SMINCUT+BIGWIG

A layout tool for optimizing timing automatically is essential for reducing the turn-around time in large-scale and high-performance LSI design. This paper describes a new timing-driven placement system called “SMINCUT+BIGWIG” which automatically produces placement results to satisfy given timing constraints.
This system is a combination of an existing placement tool called “SMINCUT” and a new timing optimization tool called “BIGWIG.” By not only optimizing placements but also re-synthesizing logic, this system can produce layouts that satisfy timing constraints in high-performance LSIs while maintaining the quality of placement. SMINCUT+BIGWIG has been integrated with embedded array LSI layout system “GLOSCAD” and is helping Fujitsu designers improve the layout design turn-around times of its large-scale LSIs.

• Large-scale Routing System: GRP

To cope with the routing of high-performance, large-scale circuits, automatic routing CAD tools must be fast and capable of handling a wide variety of conditions. The Generalized Routing Processor （GRP） is a large-scale automatic routing system for LSIs and high-density printed circuit boards. It is based on our original routing algorithm called the “Touch and Cross” method.
GRP runs on general workstations and is the successor to the Routing Processor （RP）, which is a dedicated, massively parallel computer for routing that was developed in 1992. GRP features several techniques which make it superior to RP in both routing speed and the quality of the routings it produces. It also has functions for easy handling of special routings.
This paper gives the background of GRP's development, and a brief explanation of its automatic routing technique, high-speed routing technique, and functions for special routings.

• Standard-cell-based LSI Layout System: GigaGate

CMOS fabrication technology is advancing; for example, the gates on typical chips now number in the millions. GigaGate is a total layout system we developed to lay out a standard-cell-based LSI for our high-end processor. It has functions including floor-planing, placement, routing, timing analysis, and physical design rule checking.
GigaGate supports a three-level-hierarchy layout design for simultaneous layout of multiple blocks. Moreover, this system has various functions for the design constraints and features of the most advanced 0.18 μm CMOS technology. By using this system, a large-scale, high-performance LSI can be quickly laid out.

• Layout System for Embedded Array LSI: GLOSCAD

The system LSI age is now in full swing, and the development demand for large-scale, high-performance LSIs fabricated with deep sub-micron technology is increasing. To design these LSIs quickly and efficiently, we need a design methodology for large-scale data and a timing design technique that can solve timing problems without repeating layout trials. The embedded array LSI layout system “GLOSCAD” solves these problems by using the following techniques: EarlyPlan design, Timing Driven Layout, divisional layout, and hierarchical layout.
The EarlyPlan design technique solves timing problems in large-scale circuits by using the floor plan and performing timing optimization by logical synthesis. The Timing Driven Layout technique greatly reduces timing errors. The divisional layout and hierarchical layout techniques enable concurrent design of the logic and layout of LSI.
These techniques can reduce design times by about 4/5 when compared to existing techniques. Also, they enable mounting design of LSIs with more than 20,000,000 gates. This paper introduces these techniques.

• Static Timing Analysis Tool: Gista

Timing is becoming very important in VLSI design, especially for System On Chip （SOC） design. This paper introduces the Gista static timing analysis tool, which supports the timing design of VLSIs.
Gista has been developed to manage a large circuit of about one million gates. It can quickly calculate the timing values of more than 10 million signal propagation paths and notify the designer of the presence or absence of timing errors and the paths which have timing errors. It uses the static timing analysis method to realize exhaustive checking of a large circuit. It also realizes high-speed path tracing and automatic detection of the worst condition for a complicated clock tree. Gista makes timing analysis easier and is used by Fujitsu to check various chips it designs.

• Power Mesh Analysis System: POWER

This paper introduces the POWER system, which determines optimum power bus configurations by analyzing voltage drops （IR drops） and bus deterioration due to electromigration caused by overcurrents. The POWER system is used in the floor-plan stage in cooperation with the SCCAD and GLOSCAD LSI layout systems.
This system calculates power consumption, generates a power bus resistance mesh, and analyzes voltage drops and current densities to create power bus designs that are within the limits set for voltage drops and current densities.
In the power consumption calculation, POWER uses an original modeling method to statically calculate current. In the resistance mesh generation, it generates a virtual resistance mesh for blocks before layout. In the voltage drop and current density analysis, it determines the best power bus width by repeatedly analyzing and adjusting it.
This system guarantees the reliability of the power bus at an early stage of LSI design and minimizes the percentage of total chip area which the power bus occupies.

• High-density Printed Circuit Board Noise Analysis System: SIGAL

The densities and speeds of some printed circuit boards （PCBs） are now so high that circuit malfunctions caused by noise are becoming a serious problem. Noise countermeasures can take a lot of time to design, which often causes delays in PCB design schedules. This situation has led to urgent requests by PCB designers for an accurate noise analysis system. This paper introduces SIGAL, which was developed to meet these requests.
SIGAL displays noise waveforms by considering circuit timings and automatically checks analytical results. Its design environment can be used concurrently in cooperation with a circuit design system and a component location/wiring design system. This paper uses example applications to show how SIGAL reduces PCB design hours and the number of manufacturing iterations.

• Data Processing System for Block Exposure: BEXELWIN

Before mass production of 0.13 μm-rule devices can start, large amounts of exposure data will need to be accurately and quickly obtained through full use of simulation. Simulation will therefore be an important process for handling the changes in process development techniques.
Fujitsu is using a block exposure data processing system called “BEXELWIN” for 0.13 μm-rule semiconductors. This system can efficiently reduce process times by dividing the pattern data of a semiconductor into 100 blocks and irradiating each block with electron beams simultaneously with a block exposure device （F5120 manufactured by Advantest Corporation）. This paper describes the functions of BEXELWIN.
BEXELWIN can be used to manufacture logic with about 10 million gates and is already on the market.

• CAD System for Designing Communication Devices: TCAD

New communication technologies such as ATMs and CDMAs are making communication devices faster and more versatile. However, to keep up with the pace of development, further reductions in product development periods are requested. Therefore, our department has developed the total design environment “TCAD” for more efficient design of communication devices.
In system design, a top-down design method is adopted to construct a seamless design and verification environment for the phases from specification examination to detail design. In LSI design, the register transfer level （RTL） description rules and an environment in which to analyze them are established. In PCB high-speed signal design, constraint annotation rules are established and automation of wiring design based on these rules is realized. Because TCAD integrates all of these functions, it is widely used by designers of communication devices to prevent design iteration, reduce design periods, and improve design quality.
This paper reports on solutions featuring the TCAD system in the fields of system design, LSI design, and PCB high-speed signal design.

• CAD Research at FLA

Since its establishment, Fujitsu Laboratories of America Inc. （FLA） has been conducting important research on Computer Aided Design （CAD） techniques for digital systems. Among other themes, FLA has been investigating formal design verification at various design levels, the integration of logic synthesis and layout processes, and design support for higher level design stages.
This paper gives an overview of the principal research conducted up to now and FLA's future research plans. The results of research on formal verification technology have already been applied in the ASSURE tool, and the results of research on layout-driven circuit optimization are being applied in the BIGWIG tool. We expect to see many more applications of FLA research in the future.

• Hardware of VPP5000 Series Vector-parallel Supercomputer Systems

This paper describes the hardware of the VPP5000 series of vector-parallel supercomputer systems for high-speed scientific calculations. The VPP5000 series are upward compatible with the current vector-parallel architecture and expand on it to improve performance. The series uses 64-bit addressing to enable large-volume data processing.
This series can comprise any number of 9.6 GFLOP processing elements （PEs） from 1 to 512, so it can cover the very wide performance range from 9.6 GFLOPS to 4.9 TFLOPS. Its I/O system employs a PCI bus （high-speed standard interface）, so it can be connected to high-speed devices and used to configure high-speed networks.

• Operating System of VPP5000 Series Vector-parallel Supercomputer Systems

Since 1995 Fujitsu has provided the VX/VPP300/VPP700 series to enable ultra-high-speed processing of scientific calculations. We have now developed the VPP5000 series in response to the continuing need for higher capacity and calculation speed.
This paper describes the 64-bit addressing, new file system, and network functions developed for the UXP/V V10 operating system of the VX/VPP300/VPP700 series and its successor, the UXP/V V20 operating system of the VPP5000 series. Then, it describes the enhanced capacities and processing speeds that have been achieved through these features. Lastly, it explains how UXP/V V10 functions have been upgraded to further improve computer center operations such as batch scheduling and system/job monitoring functions that employ web technology.

• Language Processing System of VPP5000 Vector-parallel Supercomputer

The VPP5000 follows the VPP300/700 series as the latest series of 3rd generation vector-parallel supercomputers. Its language processing system, which is a further enhancement of the one that has evolved with the preceding VPP machines, is designed for higher capacities and calculation speeds, flexibility in meeting user needs, and ease of use.
The language processing system consists of language compilers, message passing libraries （MPLs）, development support environments for VPP systems and workstations, and mathematics libraries. The language compiler features high-performance, a variety of functions, conformance with various standards, and upward compatibility. Its High Performance Fortran （HPF） is a data parallel language that is now being promoted as a standard in Japan. Its processing system achieves parallelism in stages and enables high-performance tuning. The support environment has abundant debugging functions for vector serial, data parallel, and MPL parallel processing. The vector and parallel algorithms in the mathematics libraries have been highly tuned for a variety of application areas, programming languages, and processing models.

• Component Technology of Object Glovia

Object Glovia （Global Value Integrated Applications） is a component-based business package, the components of which have been designed based on object-oriented technology.
Its development began with an analysis of business applications in order to decide on the package functions and structural units. Next, a policy was drawn up for application architecture and customization, and analysis and design patterns were created to standardize and raise the efficiency of development activities. Implementation patterns corresponding to design patterns were provided to compensate for differences in programmer skill levels. We also developed a source generator based on CASE （Computer Aided System Engineering） tools used for the design to provide 70％ automatic generation of source code.
Through this development approach, we have achieved a high-quality, dependable performance for all functions, high productivity, and excellent customization.