Advanced Packaging

Documentation

Advanced Packaging Documentation

• Advanced Packaging Brochure

  Providing unmatched, one-stop, turnkey services for package design, simulation, assembly, and test, Fujitsu is the acknowledged global leader in advanced packaging technology, innovation, patents and manufacturing techniques, enabling our customers’products to meet market demands today and in the future.

• ASIC Packaging Fact Sheet (512KB PDF)
• Chip Scale Packages (FBGA) Fact Sheet (164KB PDF)

  Fine Pitch BGA (FBGA) is a wire bonded BGA face-up configuration package that is near chip size, low cost and fine pitch compatible.It is suitable for consumer electronics requiring lightweight and compact size. The package uses a one layer metal polyimide interposer with wire bond technology that is capable of producing 0.7 mm wire length, and optimized mold resin compound with CTE matching that of the motherboard. Package size is reduced by using short wires, 70 µ bond pad pitch and 0.5 mm ball pitch. The package is only 1.5 mm larger than chip size and is available in both fanin and fan-out design which addresses die shrink issues that occur in memory devices. The package is also manufactured with lead-free solder balls, which can be mounted at 260°C.

• Enhanced Packages (EBGA, FDH-BGA) Fact Sheet

  Enhanced BGA (EBGA) is a wire bonded, cavity down package electrically and thermally enhanced using multi-layer laminate substrate and heat spreaders. This package is offered in one and two tier type substrates. The separation of power and ground planes in two tier provides higher electrical performance. High frequencies of up to 800 MHz can be achieved using LVDS signal pairs and short wire bonding.

• Flip Chip (FC-BGA) Fact Sheet (117KB PDF)

  The Flip-Chip BGA (FC-BGA) allows for the design of advanced packaging solutions that are ideal for current and future high-speed networking and telecommunications systems. For example, to maintain signal integrity, this package features low inductance, low dielectric loss and impedance matching. It is available in a variety of substrate materials such as Organic Build-Up and Hi-CTE Glass Ceramic and can be made at ball counts ranging from 120 to 2116.
  Additionally, this package has been characterized to perform under severe thermal conditions due to its use of specially developed structural compounds.

• Flip Chip (FC-BGA) Multimedia Presentation (video)

  Flip Chip (FC-BGA) Multimedia Presentation

• Fujitsu Lead-free Package (Presentation)

  Fujitsu Lead Free Package Specification: Ecologically friendly package with lead being eliminated from its terminal-use material and improved heat resistivity.

• Stacked/Multi-Devices (Stacked MCP) Fact Sheet (149KB PDF)

  Stacked Multi-Chip Package (Stacked MCP) is one of the most suitable chip scale packages for wireless applications. Its advantage is the compact stacked chip configuration. In the Flash memory and SRAM configuration, the pin layout can accomodate a 128 MB combination.Typical package construction consists of two die back lapped down to 100µm and total package height is only 1.2 mm. Different combinations of Flash and SRAM can be mounted in this package up to package size 10.4 x 10.8mm.

• Super High Density Packaging Technologies (Presentation)

  Trends of S-MCP/SiP, Key Technologies of SiP, Stacked MCP for mobile devices, stacked MCP for logic mixtures device/SiP, Board level reliability

• Wafer Bumping Fact Sheet (494KB PDF)

  Wafer bumping services are offered as a preparatory step for flip-chip bonding or as bumping
  service alone. The types of solder bumping available include high lead solder, eutectic solder and
  lead free solder. Lead free bump, which is composed of tin-silver alloy, can meet the WEEE
  directives. Additionally, it can eliminate alpha particle sources. Fujitsu's solder bumping service is
  currently offered for 6‿and 8‿wafers, and soon 12" wafers.

• Wafer Bumping Multimedia Presentation (Video)

  Wafer Bumping Multimedia Presentation

• Wafer Level Packaging (Super CSP) Fact Sheet (144KB PDF)

  Super Chip Scale Package (SCSP) is a wafer level package that is a true chip size package. It provides a potential solution for “known good die‿, or one test point operation as compared to two. In single chip packaging, it is customary to have testing at the wafer probe and again after packaging.

• Wireless Packages (BCC and BCC++) Fact Sheet (91KB PDF)

  The size and performance characteristics of Bump Chip Carrier (BCC) package make it well suited for RF devices, wide area networks, and DWDM systems. BCC is a molded, wire-bonded, leadless Chip Scale Package, and has terminals that are thinly plated on top of the resin bumps. This technology results in a very thin package of only 0.6 mm in height. The die pads are directly connected to the bumped terminals via wire bonds. It does not require leadframes or interposers.
  The end result is the package area and mounting volumes are considerably less than comparable packages.