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Technology Backgrounder
The Fujitsu 56GSa/s Analog-to-Digital Converter Enables 100GbE Transport
Fujitsu Microelectronics America, Inc.
May 2010
| Introduction to Analog-to-Digital Converter for 100Gbps Systems | 1 |
| The Drive Towards a Single-Chip CMOS ADC DSP | 1 |
| 56GSa/s CMOS ADC Challenges | 2 |
| CHArge-mode Interleaved Sampling (CHAIS) ADC | 2 |
| DSP and Integration Issues | 3 |
| The Fujitsu Solution | 4 |
| Development Kits | 5 |
| Conclusion | 5 |
Introduction
A 100Gbps coherent receiver needs four 56GSa/s Analog-to-Digital Converters (ADCs) and a tera-OPS DSP that dissipates only tens of watts. This paper discusses the forces pushing towards a single-chip CMOS solution. The paper also introduces the Fujitsu ultra-fast CMOS ADC, which provides the enabling technology for 100Gbps Ethernet and OTU-4 transport systems using coherent receivers.
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All Rights Reserved, Copyright © Fujitsu Microelectronics America, Inc. 2009
