Super-High-Speed 56GSa/s Analog-to-Digital Converter

The Fujitsu super-high-speed CMOS ADC provides the enabling technology for upcoming telecommunication applications such as 100G Ethernet and OTU-4 transport systems using coherent receivers. The ADC uses Fujitsu’s revolutionary CHArge-mode Interleaved Sampler technology (CHAIS), which allows the implementation of extremely fast, high-resolution ADCs in CMOS process technology.

Major benefits of the CHAIS ADC are low power consumption and the capability of integrating tens of millions of gates onto the same die using Fujitsu’s standard 65nm CMOS process technology. In combination with Fujitsu’s leading flipchip packaging technology, the super-high-speed ADC is ideal for applications that require high-performance analog and digital processing power while maintaining a reliable and proven manufacturing flow.

Evaluation board

The 56GSa/s ADC evaluation board (BATBOARD) allows early silicon characterization of Fujitsu’s CHAIS ADC technology, and provides very fast data capture for high-speed signals. With two channels of 56GSa/s 8-bit ADCs packaged in a single ROBIN device, the evaluation board provides unique features to simplify measurement and evaluation in the lab. The board is ideal for prototyping next-generation test and measurement systems as well as for testing new communication technologies.

PDF White paper: 56GSa/s ADC Enables 100GbE Transport

Product Data

PDF Fact sheet Super-High-Speed ADC

PDF Fact sheet 56GSa/s 8-bit ADC Development Kit

PDF Reality Check: Challenges of mixed-signal VLSI design for high-speed optical communications