DESCRIPTION

The FR family is a standard single-chip microcontroller incorporating various I/O resources and bus control mechanism to perform high-performance/high-speed CPU processing using a 32-bit high-performance RISC CPU. This product is in the FR65E series based on the FR30/40 family CPU with enhanced bus access. This product is a single-chip-oriented microcontroller incorporating a full range of peripheral resources (internal peripherals).

FEATURES

• FR-CPU
  
  • 32-bit RISC, load/store architecture, and 5-stage pipeline
  • Maximum operating frequency: 50 MHz, [when PLL used at original oscillation (max.) of 12.5 MHz]
  • 16-bit fixed-length instruction (basic instruction); 1 instruction/cycle
  • Memory-to-memory transfer instruction, bit manipulation instruction, barrel shift instruction, etc., suiting for built-in applications.
  • Function entry/exit instruction, register contents multi-load/store instruction, supporting high-level languages
  • Register interlock function, facilitating description in assembler language
  • Built-in multiplier supported at instruction level
    
    • Signed 32-bit multiplication: 5 cycles
    • Signed 16-bit multiplication: 3 cycles
  • Interrupt (PC and PS saved): 6 cycles, 16 priority levels
  • Harvard architecture enabling concurrent program and data access
  • Linear access to large memory space of 4 Gbytes
  • Instruction compatibility with other products of FR family
• Bus interface
  
  • Maximum operating frequency: 25 MHz
  • 24-bit address full output (16 MB space)
  • 8-/16-bit data output
  • Built-in prefetch buffers
  • Unused data/address pins used as general-purpose I/O ports
  • Chip select output for 4 completely independent areas set in min. units of 64 KB
  • Support for various memory interfaces
  • SRAM and ROM/FLASH
  • Page mode FLASHROM and Page mode ROM interface
  • Basic bus cycle: 2
  • Automatic wait cycle generation mechanism programmable for each area with wait insertion
  • External wait cycles generated by RDY input
  • DMA Supports flyby transfer which enable independent I/O wait control
• Internal memory (Memory-capacity-expanded products and the memory configuration are under review.)
• DMAC (DMA Controller)
  
  • Up to 5 channels can operate simultaneously. (For data transfer between external pins, up to 3 channels can operate simultaneously.)
  • Three transfer factors (external pin, internal peripheral, and software)
  • The activation trigger can be selected by software. (DMAC can be activated from UART0, UART1, or UART2.)
  • Addressing mode: 32-bit full-address specification (increase, decrease, and fixed)
  • Various transfer modes (demand transfer, burst transfer, step transfer, and block transfer)
  • Flyby transfer support (between external I/O and memory)
  • Selectable transfer data sizes of 8, 16, and 32 bits
  • Multiple bytes can be transferred (software determines whether or not to transfer).
  • The DMAC descriptor is an I/O area (200H to 240H; 1000H to 1024H).
• Bit search module (REALOS is used)
  
  • The position of the first change bit 0 or 1 is searched from MSB in 1 word.
• Various Timers
  
  • 16-bit reload timer, 4 channels (including 1ch for REALOS)
  • Any of 2-/8-/32-devided frequency can be selected for the internal clock. (In addition 64-/128-devided frequency can be selected only for the channel 3)
  • 16-bit free-run timer (1 channel), output compare (8 channels), input capture (4 channels)
  • 16-bit PPG timer (6 channels)
• UART
  
  • UART full-duplex double buffers
  • Five channels
  • Provision of a parity bit can be selected.
  • Asynchronous (start-stop synchronization) communications or clock-synchronous communications
  • A timer for dedicated baud rates is built in.
  • External clocks used as transfer clocks
  • A full range of error detection functions is provided.(Parity, frame, and overrun)
  • 115 Kbps is supported.
• SIO
  
  • Serial transfer of 8-bit data.
  • 3 channels.
  • Shift clock selected from three internal shift clocks and one external shift clock.
  • Shift direction switchable between LSB and MSB
• Interrupt Controller
  
  • 17 external interrupt pins (1 mask-disabled interrupt pin + 16 normal interrupt pins) These 17 pins can be used as wake-up pins at stop.
  • Interrupts from internal peripherals.
  • Programmable priority levels (16 levels) for interrupts other than non-maskable interrupts
• D/A Converter
  
  • 8-bit resolution, 3 channels
• A/D converter
  
  • 10-bit resolution, 12 channels
  • Series-to-parallel conversion; target conversion time: approx. 1.5 ms.
  • Conversion mode (one-shot; continuous).
  • Trigger (software, external, peripheral interrupts).
• Other interval timers/counters
  
  • 8-/16-bit up down counter.
  • 16-bit timer – 4 channels (U-TIMER).
  • Watchdog timer.
• I2C bus interface (400 Kbps supported)
  
  • Transmission/reception of 1-ch master/slave.
  • Arbitration function, clock synchronization function.
• I/O port
  
  • 3-V I/O port (However, 16 ports that can also serve as external interrupt pins support 5 V.)
  • 126 ports max.
• Other Features
  
  • Clock source oscillation circuit and PLL multiplier
  • INITX Reset pin (CPU operates immediately after reset via INITX pin without oscillation stabilization wait)
  • Watchdog timer and software resets
  • Stop and sleep low-power-consumption modes
  • Low-power-consumption operation (32 KHz CPU)
  • Gear function
  • Time-base timer
  • Package: LQFP-176 (· · · · · · 0.50 mm)
  • CMOS (0.35 mm)
  • Power supply 3.3 ±0.3 V
• Note: * I2C patent license

DOCUMENTATION

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PDF Datasheet V3-00 (134 pages, 1384 KB)

PDF Hardware Manual V2-00 (628 pages, 11677 KB)

PDF Hardware Manual Corrections V1-00 (1 page, 16 KB)