Microcontrollers
F²MC-8L CPU-Core Architecture
CPU-Core Features
• 8-bit CPU core
• Highly efficient instruction set
• Two 16-bit accumulators with A-T
• Architecture
• Data operation: 1/8/16 bit
• Enhanced bit manipulation: Clear set and test bit F²MCpower-saving modes
• 64Kbytes program/data memory address space
• Multiply and divide operations
F²MC Power-saving Modes
| *Where applicable ** Where a second low-speed clock is available | |
| GEAR* | Dynamic selection of CPU cycle time in four ratios (0.4, 0.8, 1.6 and 6.5µm) at 10MHz clock |
| SUB RUN** | Switch to run from sub-clock. Turn off main oscillator. |
| SLEEP | Peripheral functions are running, CPU core is in power-down. |
| CLOCK** | Only the low-speed clock and prescalar are running. |
| STOP | Chip is in complete power-down mode. |
For more information on F²MC-8FX Family Features / F²MC-16L/LX CPU-Core Architecture
