DESCRIPTION

The FUJITSU FR family of single-chip microcontrollers using a 32-bit high-performance RISC CPU, with a variety of built-in I/O resources and bus control mechanisms for built-in control applications requiring high-capability, highspeed CPU processing. External bus access is assumed in order to support the expanded address space accessible by the 32-bit CPU, and a 1 KB cache memory plus large 128 KB RAM are provided for high-speed execution of CPU instructions. This microcontroller is ideal for built-in applications such as DVD players, navigation systems, high-capability FAX and printer control that demand high-capability CPU processing power. The MB91307A is a FR65E series product based on the FR30/40 series CPU with enhanced bus access for higher speed operation.

FEATURES

• FR CPU
  
  • 32-bit RISC, load/store architecture, 5-stage pipeline
  • Operating frequency 66MHz [with PLL: base frequency 16.5 MHz]
  • 16-bit fixed length instructions (basic instructions), 1 instruction per cycle
  • Instructions for built-in applications: memory-to-memory transfer, bit processing, barrel shift etc.
  • Instructions adapted for high-level languages: function input/output instructions, register contents multi-load/ store instructions
  • Easier assembler notation: register interlock function
  • Built-in multiplier/instruction level support Signed 32-bit multiplication: 5 cycles Signed 16-bit multiplication: 3 cycles
  • Interrupt (PC, PS removal): 6 cycles, 16 priority levels
  • Harvard architecture for simultaneous execution of program access and data access
  • CPU hold 4-word queue allows advanced instruction fetch function
  • 4 GB expanded memory space enables linear access
  • Instruction compatible with FR30/40 family
• Bus interface
  
  • Operating frequency: Max. 33 MHz
  • 8- or 16-bit data output
  • Built-in pre-fetch buffer
  • Unused data/address pins can be used as general-0purpose input/output ports
  • Fully independent 8-area chip select outputs, can be set in minimum 64 KB units
  • Interface support for many memory types
    
    • SRAM, ROM/Flash
    • Page mode flash ROM, page mode ROM interface
    • Burst mode flash ROM (select burst length 1, 2, 4, 8)
  • Basic bus cycle: 2 cycles
  • Programmable by area with automatic wait cycle generation to enable wait insert
  • DMA supports fly-by transfer with independent I/O wait control
• Built-in RAM
  
  • 128 KB built-in RAM capacity
  • Accepts writing of data and instruction codes, enabling use as instruction RAM
• Instruction cache
  
  • 1 KB capacity
  • 2-way set associative
  • 4-words (16 bytes) per set
  • Lock function enables permanent program storage
  • Areas not used for instruction cache can be used for RAM
• DMAC (DMA controller)
  
  • 5-channel (3-channel external-to-external)
  • 3 transfer sources (external pin, internal peripheral, software)
  • Addressing mode with 32-bit full address indication (increment, decrement, fixed)
  • Transfer mode (demand transfer / burst transfer / step transfer / block transfer)
  • Fly-by transfer support (3 channels between external I/O and external memory)
  • Transfer data size selection 8/16/32-bit
• Bit search module (using REALOS)
  
  • Searches words from MSB for first bit position of a 1/0 change
• Reload timer (includes 1 channel for REALOS)
  
  • 16-bit timer: 3 channels
  • Internal clock multiplier choice of x2, x8, x32
• UART
  
  • Full duplex double buffer
  • 3-channel
  • Parity/no parity selection
  • Asynchronous (start-stop synchronized), CLK-synchronized communications selection
  • Built-in exclusive baud rate timer
  • External clock can be used as transfer clock
  • Variety of error detection functions (parity, frame, overrun)
• I2C interface
• Interrupt controller
  
  • Total of 9 external interrupts: 1 non-maskable interrupt pin (NMI) and 8 normal interrupt pins INT7-INT0 Interrupt from internal peripheral devices
  • Programmable priority settings (16 levels) enabled, except for non-maskable interrupt
  • Can be used for wake-up from stop mode
• A/D converter
  
  • 10-bit resolution, 4-channel
  • Sequential comparator type, conversion time approx. 5.4 ms
  • Conversion modes: single conversion mode, continuous conversion mode
  • Startup source: software / external trigger / timer output signal
• Other interval timers
  
  • 16-bit timer with 3 channels (U-timer)
  • Watchdog timer
• I/O port
  
  • Maximum 69 ports
• Other Features
  
  • Built-in oscillator circuit for clock source, PLL multiplier selection enabled
  • INIT reset pin
  • Also included: watchdog timer reset, software reset
  • Power-saving modes: stop mode, sleep mode supported
  • Gear functions
  • Built-in time base timer
  • Packages: LQFP-120 (FPT-120P-M21)
  • CMOS technology: 0.25 mm
  • Supply voltage: 3.3 V ± 0.3 V (built-in regulator 3.3 V ® 2.5 V)
  • Master/slave sending and receiving • Arbitration function
  • Clock synchronization function • Slave address/general call address detection function
  • Transfer direction detection function • Start condition repeat generator and detection function
  • Bus error detection function • 10-bit/7-bit slave address
  • Operates in standard mode (Max. 100 Kbps) or high speed mode (Max. 400 Kbps)
• Package
  
  • 120-pin, plastic LQFP
• Note: Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent rights to use these components in an I2C system provided that the system conforms to the I2C Standard Specification as defined by Philips.

DOCUMENTATION

Note: The use of Adobe® Acrobat Reader is recommended to have all download and browsing features available for pdf files.

PDF Datasheet V3-00 (87 pages, 892 KB)

PDF Datasheet V2-00 (96 pages, 894 KB)

PDF Hardware Manual V6-00 (522 pages, 5803 KB)

PDF Hardware Manual Errata V1-00 (1 page, 7 KB)