DESCRIPTION

The MB91108 is a standard single-chip microcontroller constructed around the 32-bit RISC CPU (FR familyNote) core with abundant I/O resources and bus control functions optimized for high-performance/high-speed CPU processing for embedded controller applications. To support the vast memory space accessed by the 32-bit CPU, the MB91108 normally operates in the external bus access mode and executes instructions on the internal 1 Kbyte cache memory and 160 Kbytes RAM for enhanced performance. The MB91108 is optimized for applications requiring high-performance CPU processing such as navigation sys-tems, high-performance FAXs and printer controllers. Note: FR Family stands for FUJITSU RISC controller.

FEATURES

• FR CPU
  
  • 32-bit RISC, load/store architecture, 5-stage pipeline
  • Operating clock frequency: Internal 50 MHz/external 25 MHz (PLL used at source oscillation 12.5 MHz)
  • General purpose registers: 32 bits x 16
  • 16-bit fixed length instructions (basic instructions), 1 instruction/1 cycle
  • Memory to memory transfer, bit processing, barrel shifter processing: Optimized for embedded applications
  • Function entrance/exit instructions, multiple load/store instructions of register contents, instruction systems supporting high level languages
  • Function entrance/exit instructions, multiple load/store instructions of register contents, instruction systems supporting high level languages
  • Branch instructions with delay slots: Reduced overhead time in branch executions
  • Internal multiplier/supported at instruction level:
    
    • Signed 32-bit multiplication: 5 cycles
    • Signed 16-bit multiplication: 3 cycles
  • Interrupt (push PC and PS): 6 cycles, 16 priority levels
• Bus interface
  
  • Clock doubler: Internal 50 MHz, external bus 25 MHz operation
  • 25-bit address bus (32 Mbytes memory space) 8/16-bit data bus Basic external bus cycle: 2 clock cycles
  • Chip select outputs for setting down to a minimum memory block size of 64 Kbytes: 8 Interface supported for various memory technologies
  • Chip select outputs for setting down to a minimum memory block size of 64 Kbytes: 8 Interface supported for various memory technologies
• DRAM interface (area 4 and 5)
  
  • Automatic wait cycle insertion: Flexible setting, from 0 to 7 for each area
  • Unused data/address pins can be configured us input/output ports
  • Little endian mode supported (Select 1 area from area 1 to 5)
• DRAM interface
  
  • 2 banks independent control (area 4 and 5)
  • Double CAS DRAM (normal DRAM I/F) / Single CAS DRAM / Hyper DRAM
  • Basic bus cycle: Normally 5 cycles, 2-cycle access possible in high-speed page mode
  • Programmable waveform: Automatic 1-cycle wait insertion to RAS and CAS cycles
  • DRAM refresh
• CBR refresh (interval time configurable by 6-bit timer): Self-refresh mode
  
  • Supports 8/9/10/12-bit column address width
  • 2CAS/1WE, 2WE/1CAS selective
• Cache memory
  
  • 1-Kbyte instruction cache memory
  • 2 way set associative
  • 32 block/way, 4 entry(4 word)/block
  • Lock function: For specific program code to be resident in cashe memory
• DMAC (DMA controller)
  
  • 8 channels
  • Transfer incident/external pins/internal resource interrupt requests
  • Transfer sequence: Step transfer/block transfer/burst transfer/continuous transfer
  • Transfer data length: 8 bits/16 bits/32 bits selective
  • NMI/interrupt request enables temporary stop operation
• UART
  
  • 3 independent channels
  • Full-duplex double buffer
  • Data length: 7 bits to 9 bits (non-parity), 6 bits to 8 bits (parity)
  • Asynchronous (start-stop system), CLK-synchronized communication selective
  • Multi-processor mode
  • Internal 16-bit timer (U-TIMER) operating as a proprietary baud rate generator: Generates any given baud rate Use external clock can be used as a transfer clock
  • Error detection: Parity, frame, overrun
• 10-bit A/D converter (successive approximation conversion type)
  
  • 10-bit resolution, 4 channels
  • Successive approximation type: Conversion time of 5.6µs at 25 MHz
  • Internal sample and hold circuit
  • Conversion mode: Single conversion/scanning conversion/repeated conversion selective
  • Start: Software/external trigger/internal timer selective
• 16-bit reload timer
  
  • 16-bit timer: 3 channels
  • Internal clock: 2 clock cycle resolution, divide by 2/8/32 selective
• Other interval timers
  
  • 16-bit timer: 3 channels (U-TIMER
  • PWM timer: 4 channels
  • Watchdog timer: 1 channel
• Bit search module: First bit transition "1" or "0" from MSB can be detected in 1 cycle
• Interrupt controller
  
  • External interrupt input: Non-maskable interrupt (NMI), normal interrupt 8 (INT0 to INT7)
  • Internal interrupt incident:UART, DMA controller (DMAC), A/D converter, U-TIMER and delayed interrupt module
  • Priority levels of interrupts are programmable except for non-maskable interrupt (in 16 levels)
• Others
  
  • Reset cause: Power-on reset/hardware standby/watchdog timer/software reset/external reset
  • Low-power consumption mode: Sleep mode/stop mode
  • Clock control
  • Gear function: Operating clocks for CPU and peripherals are independently selective
  • Gear clock can be selected from 1/1, 1/2, 1/4 and 1/8 (or 1/2, 1/4, 1/8 and 1/16) However, operating frequency for peripherals is less than 25 MHz.
• Packages: LQFP-120
• CMOS technology (0.35µm):
  
  • MB91V108 (0.35µm) Development model
  • MB91108 (0.25µm) Production model
• Power supply voltage: 3.3 V ± 0.3 V (internal regulator)

DOCUMENTATION

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PDF Datasheet V3-00 (96 pages, 1343 KB)

PDF Hardware Manual V2-00 (455 pages, 6443 KB)

PDF Package FPT-120P-M21 (1 page, 50 KB)