DESCRIPTION

The MB90340-series with up to two FULL-CAN interfaces (MB90V340: 3ch) and FLASH ROM is especially designed for automotive and industrial applications. Its main feature are the on board CAN Interfaces, which conform to V2.0 Part A and Part B, while supporting a very flexible message buffer scheme and so offering more functions than a normal full CAN approach. With the new 0.35 um CMOS technology, Fujitsu now offers on-chip FLASH-ROM program memory up to 384 Kbytes. An internal voltage booster removes the necessity for a second programming voltage. An on board voltage regulator provides 3 V to the internal MCU core. This creates a major advantage in terms of EMI and power consumption.

The internal PLL clock frequency multiplier provides an internal 42 ns instruction cycle time from an external 4 MHz clock. The unit features an 8 channel Output Compare Unit and 8channel Input Capture Unit with two separate 16-bit free running timers. 4 USART (MB90V340: 5 USART) constitute additional functionality for communication purposes

The F²MC-16LX CPU core instruction set retains the AT architecture of the F²MC *1 family, with additional instructions for use with high-level languages, expanded addressing mode, enhanced multiply and divide instructions, and full bit processing. Also included is a built-in 32-bit accumulator for long-word processing.

Note
*1: F²MC is an abbreviation for FUJITSU Flexible Microcontroller, and is a registered trademark of FUJITSU, Ltd.

FEATURES

• 16-bit core CPU; 4 MHz external clock (24 MHz internal, 42 ns instr. cycle time)
• New 0.35 µm CMOS Process Technology
• Internal voltage regulator supports 3 V MCU core, offering low EMI and low power consumption figures
• Up to two FULL-CAN interfaces (MB90V340: 3ch); conforming to Version 2.0 Part A and Part B, flexible message buffering (mailbox and FIFO buffering can be mixed)
• Powerful interrupt functions (8 progr. priority levels; 16 external interrupts)
• EI2OS - Automatic transfer function independent of CPU; 16 ch. of intelligent I/O Services
• DMA
• 18-bit Time-base counter
• Watchdog Timer
• 4 full duplex USART (SCI/LIN) (MB90V340: 5 USART)
• Up to 2 ch I²C with 400 kbit/s
• A/D Converter : 16 ch to 24 ch. analog inputs (Resolution 10 bits or 8 bit, conversion time 3µs)
• 16-bit reload timer×4 ch
• ICU (Input capture) 16 bit×8 ch
• OCU (Output capture) 16 bit×8 ch
• 16-bit free running timer×2 ch (FRT0 : ICU 0/1/2/3, OCU 0/1/2/3, FRT1 : ICU 4/5/6/7, OCU 4/5/6/7)
• 8/16-bit Programmable Pulse Generator 8ch×16-bit / 16ch×8-bit
• Optimized instruction set for controller applications (bit, byte, word and long-word data types; 23 different addressing modes; barrel shift; variety of pointers)
• 4-byte instruction execution queue
• Signed multiply (16 bit×16 bit) and divide (32 bit/16 bit) instructions available
• Program Patch Function
• Fast Interrupt processing
• Low Power Consumption - 10 different power saving modes : (Sleep, Stop, CPU intermittent mode, ...)
• 32 kHz Subsytem Clock (devices without S-suffix)
• External bus interface
• Programmable input levels (Automotive / CMOS-Schmitt (initial level is Automotive), for external bus also TTL level)
• Package : 100-pin plastic QFP and LQFP

DOCUMENTATION

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PDF MB90340E Series Data sheet V2.00 (84 pages, 1097KB)

PDF Datasheet V3-00 (84 pages, 1131 KB)

PDF Hardware Manual V2-00 (680 pages, 17406 KB)

PDF MB90340E Series Hardware Manual Rev 2.0 (8.89 MB)

PDF Hardware Manual Correction V1-01 (2 pages, 194 KB)

PDF Hardware Manual Errata V2-00 (7 pages, 53 KB)

PDF F2MC-16LX Standby Cancel Failure Documentation (25 pages, 422 KB)

PDF PF package 0.65mm QFP (1 page, 109 KB)

PDF PFV package 0.5mm LQFP (1 page, 104 KB)

PDF CR-package 299-pin Xmm PGA (1 page, 33 KB)

Parts Table

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