ASIC

Documentation

• .11µm Standard Celll Fact Sheet (151KB PDF)

  Fujitsu's CS91, a 110nm (70nm Leff ) standard-cell product, is based on Fujitsu's state-of-the-art CMOS process technology, a deep sub-micron process designed for today's high-speed and low-power SOC products. The cell library, which is optimized for synthesis-based designs, has accurate timing and power-characterized data, cell areas, and statistical wire-load models.

• .13µm node CMOS Process (CS90A) Fact Sheet (90KB PDF)

  130nm node CMOS Process (CS90A) features and technology roadmap

• .18µm Embedded Array Fact Sheet (97KB PDF)

  Fujitsu’s CE81 is a series of high performance, 0.18µm (0.13µm Leff) CMOS embedded arrays that include full support of diffused high-speed RAMs, ROMs, analog, mixed-signal macros, and a variety of embedded functions.

• .18µm node CMOS Process (CS80B) Fact Sheet (77KB PDF)

  Features: 2-Poly and 6-Metal Process, Retrograde Twin Wells on P Epi Substrate, STI(Shallow Trench Isolation), Salicided Gate, Salicided Source and Drain, CMP Planarization, CVD Filling for Via, Stackable Contact and Vias, Oxide/Nitride Passivation

• .18µm Standard Cell Fact Sheet (81KB PDF)

  Fujitsu’s CS81, a 0.18µm (0.13µm Leff) standard-cell product, is based on Fujitsu’s state-of-the-art CMOS process technology, a deep sub-micron process designed for today’s high-density and low-power SOC products. The cell library, which is optimized for synthesis-based designs, has accurate timing and power-characterized data, cell areas, and statistical wire-load models. The CS81 standard-cell library contains both high-performance and high-density cells, giving designers the option of combining both types of standard cell blocks on the same chip. The CS81 library supports popular third-party tools and data-exchange file standards.

• .25µm Embedded Array Fact Sheet (156KB PDF)

  Fujitsu’s CE71 is a series of high-performance, 0.18µm Leff CMOS embedded arrays that include full support of diffused high-speed RAMs, ROMs, mixed-signal macros, and a variety of other embedded functions.

• .25µm Standard Cell Fact Sheet (147KB PDF)

  Fujitsu’s CS71, a 0.25µm (0.18µm Leff) standard cell product, is based on Fujitsu’s state-of-the-art CMOS process technology–a process designed for high performance and high integration. The CS71 family offers up to 10 million
  gates, using as many as five layers of metal.

• "Going, Going, Gone-- Is there a place for second-tier ASIC suppliers?" ASIC and SoC Strategies Article

  Article Table of Contents

• 0.11µm CMOS Standard Cell Fact Sheet

  Fujitsu's CS91, a 110nm (70nm Leff ) standard-cell product, is based on Fujitsu's state-of-the-art CMOS process technology, a deep sub-micron process designed for today's high-speed and low-power SOC products. The cell library, which is optimized for synthesis-based designs, has accurate timing and power-characterized data, cell areas, and statistical wire-load models. The CS91 standard-cell library contains both high-performance and high-density cells, giving designers the option of combining both types of standard cell blocks on the same chip. The CS91 library supports popular third-party tools and data-exchange file standards. The CS91 chip cores can operate at 0.8V to 1.3V range. The I/Os, operating at 0.8V to 3.6V range, can conveniently interface with various types of devices. Interface options include low-swing, high-speed I/Os and high-speed
  bus interface I/Os.

• 10/100 Mbps Ethernet MAC Core Fact Sheet

  The 10/100 MAC core is part of the Fujitsu IPWare™ Library. The 10/100 MAC core is a PAUSE Flow Control Ethernet Media Access Controller (MAC) capable of both 10 and 100 Mbps data operation.

• 2.5Gbps Transceiver Macro with CDR Fact Sheet

  Fujitsu’s triple mode parallel transceiver is a physical I/O interface macro for ASICs that performs high-speed back plane data communication, operating at low power dissipation. The triple data transfer rates, 2.5G/1.25G/622M bps, can be selected depending on the system requirements.The
  macro consists of a 16-bit transmitter, and a 16-bit receiver array.The receiver macro contains CDR (Clock Data Recovery) using dual loop PLL (analog and digital PLL), that complies with SONET/SDH jitter tolerance mask, up to 72-bit run length.The Receiver has an integrated line equalization
  capability to compensate for inter-symbol-interference (ISI), which enables a wide variation in data link length and range, from short PCB trace to long twisted pair cables connections.The device also includes on-chip PRBS generators and comparators for testability.

• 2.5Gbps Transceiver Macro with CDR Fact Sheet (90KB PDF)

  Fujitsu’s triple mode parallel transceiver is a physical I/O interface macro for ASICs that performs high-speed back plane data communication, operating at low power dissipation. The triple data transfer rates, 2.5G/1.25G/622M bps, can be selected depending on the system requirements.The macro consists of a 16-bit transmitter, and a 16-bit receiver array.The receiver macro contains CDR (Clock Data Recovery) using dual loop PLL (analog and digital PLL), that complies with SONET/SDH jitter tolerance mask, up to 72-bit run length.The Receiver has an integrated line equalization capability to compensate for inter-symbol-interference (ISI), which enables a wide variation in data link length and range, from short PCB trace to long twisted pair cables connections.The device also includes on-chip PRBS generators and comparators for testability.

• 2007.5 Product Guide [ASSP/Memory/ASIC]
• 3.125Gbps Parallel CDR Transceiver (0.11µm) Fact Sheet (64KB PDF)

  Fujitsu’s parallel transceiver, is a seletable 2/4/8/16- channel CDR receiver and transmitter array intended for ASICs that perform at high bandwidth data
  communications.

• 3.125Gbps Parallel CDR Transceiver (0.18µm) Fact Sheet (417KB PDF)

  Fujitsu’s parallel transceiver, which is available in 2/4/8/16-channel width CDR receiver and transmitter arrays, is for ASICs that perform at high bandwidth data
  communications. The macro meets SONET/SDH OC-48 jitter tolerance mask requirement. The macro has 175mW/ch power dissipation (including Rx, Tx, CDR, bias circuit and PLL, maximum pre-emphasis, 16ch case) and runs under power
  supply of 1.8V±0.15V, 3.3V±0.30V and junction temperature of -40°C ~ 125°C.

• 3.125Gbps x 4 Parallel Transceiver (0.11µm) Fact Sheet (98KB PDF)

  The Fujitsu’s XAUI macro is for ASICs that perform at
  high bandwidth data communication.

• 3.125Gbps x 4 Parallel Transceiver (0.18µm) Fact Sheet (53KB PDF)

  The Fujitsu’s XAUI macro is for ASICs that perform at high bandwidth data communication.

• 90nm CMOS Standard Cell Fact Sheet (71KB PDF)

  CS101 Series, a group of 90nm standard cells, addresses the design challenges of the mobile device market in which low power consumption and multifunctionality are required. Also, the CS101 products serve the design needs of the leading-edge network devices, server applications and telecommunication equipment markets where high performance is vital.

• 90nm node CMOS Process (CS100A) Fact Sheet (276KB PDF)

  90nm node CMOS Process (CS100A) features and technology roadmap

• ARC Processor Core Fact Sheet

  ARC is comprised of a Base RISC Engine, the ARC Extension Library, the Architect, integrated test suites, multi-interface architecture, the ARC Co-design toolset, a complete software development toolchain, and both hardware
  and software emulators. Provided as a synthesizable “soft macro‿with the configuration controlled by the user through the ARC Architect test suite, the ARC architecture can be configured to meet specific performance and cost targets
  enabling customers to effectively manage their design process at the system level.

• ARM7TDMI™ Processor Core Fact Sheet

  The ARM7TDMI embedded CPU core is part of Fujitsu’s IPWare™ Library. The Fujitsu ARM7TDMI processor core, developed by ARM, is implemented in Fujitsu’s 0.25µm process technology. This core contains all of the ARM7TDMI processor features, including a 32-bit RISC engine, Thumb instruction set (smaller code size), debug functions, multiplier, and embedded ICE support logic. The ARM7TDMI processor is supported by multiple hardware and software vendors through a wide array of development tools and RTOS created by ARM.

• ASIC Mixed-Signal and Analog Macros Fact Sheet (159KB)

  To achieve the highest level ofsystem integration, Fujitsu offers avariety ofanalog and mixed-signal macros for customer use inconjunction with its Embedded Arrays and Standard Celllibraries. Data communications, networking, graphics, anddigital audio/video are among the applications that can takeadvantage ofthese mixed-signal and analog macros. Additionally,embedded RAMs, ROMs, phase-locked loops (PLLs), and otherSOC IP cores from Fujitsu’s IPWare™are provided to enablecustomers to implement system-level solutions on a single chip.

• ASIC Packaging Article

  For its ASIC customers, Fujitsu offers "one-stop shopping" for all their packaging needs. In addition to a robust set of off-the-shelf standard packages, Fujitsu offers complete inhouse turnkey package design, as well as assembly and test services. Fujitsu’s ASIC packaging solutions range from lead insertion matrix-type PGAs to surface mount Flat Quad \Lead types (QFP, LQFP, TQFP, HQFP) and Matrix types (BGAs and LGAs).

• Bluetooth™ Solution Article

  BluetoothTM is a standard for radio communication over short distances on the
  2.4GHz band. This article introduces the features of our BluetoothTM solution
  for embedded devices that conform to BluetoothTM version 1.1.

• Bluetooth™ Solution BlueA™

  Products Outline, Fujitsu Solutions for customer applications, Block Diagram

• CE61 Series Embedded Array Fact Sheet

  Fujitsu’s CE61 is a series of high-performance, CMOS embedded arrays featuring full support of mixed-signal macros, as well as diffused high-speed RAMs, ROMs and a variety of other embedded functions. The CE61 series offers density and performance approaching standard cells, yet provides the time-to-market advantage of gate arrays. The E-series is optimized for pad-limited designs, and the F-series offers a cost-effective solution for core-limited designs. A fifth
  metal layer option is also available for area bump designs, providing over 1,000 I/O pads.

• Fujitsu SOC (Presentation)

  The Fujitsu Advantage, Fujitsu Solution Platform, IPWare Library, Example of SOC Engagement Model, Methodology and Tools

• Fujitsu System Applications Support (Presentation)

  SOC Application Development Lab, Multimedia- VolP, Wireless-Bluetooth, Processors, DSP, and Peripherals- ARM Reference Platform

• Fujitsu VoIP

  Custom-designed voice DSP •Consumer applications •Highly scalable •Single & multiple channels •High performance •Low power •Synthesized for: 0.25µm, 0.18µm, 0.11µm

• High Performance ASIC Solutions for the Metro & Long Haul Markets (Presentation)

  Business Strategy, Target Markets, Products- Process Technology, Packaging Roadmap, High-Speed I-O Offerings Current Advanced ASICs, Case Study

• High-speed Interface Technology for Image Data Transmission (332KB PDF)

  Fujitsu Find Magazine: Vol.26 No.1 2008

• IP-Phone Chip Fact Sheet

  Fujitsu’s IP-Phone chip offers a comprehensive software package with a reference design that provides a complete and cost-effective solution. This fully integrated solution has a DSP engine, RISC host processor, Ethernet switch, and a rich set of peripherals. It simultaneously supports multiple channels of voice and fax and runs any combination of speech Vocoder algorithms, telephony functions, and fax relay. The DSP core is based on a customized RISC-DSP combo core, along with a hardware accelerator (co-processor) for performance enhancements.

• LCOS Backplane Process Fact Sheet (117KB PDF)

  LCOS Backplane Process features, CMOS Image Sensor Process features, High Voltage Process

• MB86C00/MBG011 Bluetooth™ Baseband LSI Fact Sheet

  MB86C00/MBG011 BluetoothTM Baseband LSI provides all the digital base band signal processing and protocol hardware to complement the functionality of external BluetoothTM RF IC.

• PCI Peripheral Core Fact Sheet

  The PCI Synthesizable Core is a part of the Fujitsu IPWare™ Library. The Fujitsu PCI Cores are RTL synthesizable modules that provide an interface between an application and the PCI bus. All PCI protocol and timing requirementsare handled by the core, which is controlled through a simple application interface.
  

• SERDES Framer Interface Level-4 Fact Sheet (38KB PDF)

  Fujitsu's SFI4-1.0 macro enables the interface of any two chips at an aggregate of 10 to 12.5Gbps in each direction. Sixteen 622/780 Mbps differential data lines (plus one clock) are provided in the transmit direction, and another sixteen
  (plus one clock) in the receive direction.

• SERDES Framer Interface Level-5 Fact Sheet (47KB PDF)

  Fujitsu’s SFI-5 compliant transceiver macro is a 17- channel physical I/O interface macro for ASICs that perform high bandwidth data communication while operating at low power consumption. The transceiver consists of a 17-channel transmitter unit, a 17-channel receiver unit and a bias unit. The transmitter and the receiver are compliant with OIF SFI-5 specification.

• SoC Design Environment RDF V3.0 that Supports Low-power Designs (312KB PDF)

  Fujitsu Find Magazine: Vol.26 No.1 2008

• System Packet Interface Level-4 Fact Sheet (31KB PDF)

  The SPI-4 interface core enables the interconnection of physical layer devices to link layer devices in 10Gb/s POS, ATM, and Ethernet applications.
  

• USB 2.0 Device Controller Macro Fact Sheet

  – Link
  • Protocol Engine (UDC-20) is a fully synthesizable soft core that supports high-speed (480 Mbps), full-speed (12Mbps) and low-speed (1.5Mbps) signaling bit rates.
  • UTMI (USB 2.0 Transceiver Macrocell Interface) enables connection with discrete PHY chip (ASSP) as well as integrated PHY.
  • Protocol engine reduces CPU burden by processing basic USB 2.0 protocols in hardware.
  

• USB Function Core Fact Sheet

  The USB Function Core is a synthesizable core and is part of the Fujitsu IPWare™ Library. This core is fully compliant with revision 1.0 of the USB specification.

• USB Host Controller Core Fact Sheet

  The USB Host Controller is a synthesizable core and is part
  of the Fujitsu IPWare™ Library.

• Utopia Level II / I Interface Core Fact Sheet

  The Utopia Level II interface provides a standard interface between a single ATM layer device and multiple PHY layer devices. The macro can also be configured as a Utopia Level 1 interface, which is used to provide a standard interface between a single ATM layer device and a single PHY layer device. The macro may be used in either ATM Layer or PHY Layer mode. Eight or 16-bit Utopia data is supported. The macro also performs data flow control between the two layers: parity checking and port address/poll address routing.

• VOIP CODEC Fact Sheet

  VoIP Codec is designed for implementing speech Vocoders to support VOIP applications for Customer Premises Equipment (CPE). Up to 4 channels of audio can be supported simultaneously. The current implemented Vocoders are G.711, G.726, G.728, G.729AB, and G.729E. Any combination of Vocoders is supported and each channel provides echo cancellation (G.168), DTMF generation/detection, and jitter buffering. The DSP engine is based on ARC-3 Processor utilizing its DSP
  extensions together with extensive hardware accelerators (Co-Processor). This provides a flexible and powerful soft solution for future algorithm enhancements and upgrades. Test chip is offered as a Soft Core Silicon for ASIC & SOC designs. A top-level block diagram of the chip is shown above.