ASIC

Methodology - LSI Timing Driven Layout

• Restriction on chip level can be altered for each level of design.
• Top-down timing takes into consideration the timing restrictions at each design level.
• Full-fledged implementation of the forward-annotation concept can eliminate post-layout timing issues.
• By eliminating post-layout returns, design TAT can be substantially reduced.
• An ideal top-down stage design is possible by optimizing the timing budget for the lower-stage modules.
• Fujitsu offers an integrated layout environment, ranging from automatic generation of variable frames through to final verification.
• Features contributing to the timing driven layout flow include:
  
  • Power-supply wiring-planning function for the floor-planning stage
  • Timing-driven design methodology
  • Fully automatic clock-generation system
  • Static or dynamic current analysis and verification system for precise verification of current density, voltage drop and cross-talk effects
  • Layout system that takes signal integrity into account
  • Automatic correction for post-layout timing errors
  • Optimal scan-chain generation based on layout information

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Related Links

• System LSI Design Flow
  
  • HW/SW Co-Simulation
  • Emulation
  • Total Development TAT
  • Low Power Design
  • Logic Verification
  • Static Timing Analyzer
  • Formal Verification
• System LSI Test Interface Flow
  
  • Test CAD Flow
  • Test Synthesis
• System LSI Timing Driven Layout Flow
  
  • Hierarchical vs. Flat
  • Floorplan & Synthesis Link
  • I/O Frame Generation
  • Automatic Clock Tree Synthesis
  • 3D RC Extraction
  • Current Analysis
  • Signal Integrity
  • Deep-Submicron High-Precision Delay Model