ASIC

Methodology - System LSI Design Flow

• As system LSIs become larger and more complex, high-end design effectiveness becomes increasingly important.
• Design interface levels are rising above Netlist and RTL.
• By providing a methodology for high-end design (which occupies between 70% and 80% of the overall development time, and by using design methods that take leading-edge ASIC technologies into account, Fujitsu offers its customers optimal, application-specific solutions.

1. Function, algorithm and architecture verification (hardware and software partitioning)
2. Performance estimation (system performance, area, timing, power requirements)
3. Highly precise, Super Turnaround Time (TAT) CAD system

---

Related Links

• System LSI Design Flow
  
  • HW/SW Co-Simulation
  • Emulation
  • Total Development TAT
  • Low Power Design
  • Logic Verification
  • Static Timing Analyzer
  • Formal Verification
• System LSI Test Interface Flow
  
  • Test CAD Flow
  • Test Synthesis
• System LSI Timing Driven Layout Flow
  
  • Hierarchical vs. Flat
  • Floorplan & Synthesis Link
  • I/O Frame Generation
  • Automatic Clock Tree Synthesis
  • 3D RC Extraction
  • Current Analysis
  • Signal Integrity
  • Deep-Submicron High-Precision Delay Model