A 100Gbps coherent receiver needs four 56GSa/s Analog-to-Digital Converters (ADCs) and a tera-OPS DSP that dissipates only tens of watts. This paper discusses the forces pushing towards a single-chip CMOS solution. The paper also introduces the Fujitsu ultra-fast CMOS ADC, which provides the enabling technology for 100Gbps Ethernet and OTU-4 transport systems using coherent receivers.
Advanced ASIC (Application Specific Integrated Circuit) development today requires complex and expensive design tools, leading-edge process technologies, and experienced engineering teams. Some large companies can commit the resources needed to acquire the expertise, support a sizable design team, and invest in the complete tool chain and development flow, all the way from circuit design to Graphic Data Systems (GDS) and beyond. This option, known as Customer Owned Tooling (COT), is a good choice for companies that can amortize costs over many products that are manufactured in high volumes for broad markets.
It is now possible to handle high-resolution data in consumer products such as full HD flat-screen TVs. As such, the transmission of large volumes of data between and inside these devices is required. However, various problems have arisen in data transmission using the legacy CMOS interface, revealing its limits. This article presents various high speed interface technologies that are beginning to be adopted in order to replace it.
Recently, the demand for low power consumption LSIs has been increasing constantly. In concurrence with process miniaturization, the leak current emitted while the transistor is OFF has been increasing and has now reached a level where it can no longer be ignored in products in which battery lifetime is important, such as mobile products. In this context, Fujitsu has released RDF v3.0, which includes a function to facilitate low-power design in our conventional LSI Design Flow RDF. This article introduces the low-power technology supported by RDF v3.0.
The Fujitsu's Analog-to-Digital Converter (ADC) IP is designed to provide high efficiency and ultra-low power for various mixed-signal applications, including portable ultrasound devices, mobile basebands, TV demodulators, industrial automation and robotics
Fujitsu’s CE81 is a series of high performance, 0.18µm (0.13µm Leff) CMOS embedded arrays that include full support of diffused high-speed RAMs, ROMs, analog, mixed-signal macros, and a variety of embedded functions.
Fujitsu’s CE71 is a series of high-performance, 0.18µm Leff CMOS embedded arrays that include full support of diffused high-speed RAMs, ROMs, mixed-signal macros, and a variety of other embedded functions. The CE71 series offers density and performance similar to those of standard cells, yet provides the time-to-market advantage of gate arrays. The CE71 series devices include 44µm, 66µm, or 88µm pad pitch for a cost-effective solution for both pad-limited and core-limited designs.
Fujitsu’s triple mode parallel transceiver is a physical I/O interface macro for ASICs that performs high-speed back plane data communication, operating at low power dissipation. The triple data transfer rates, 2.5G/1.25G/622M bps, can be selected dependi
Fujitsu’s parallel transceiver, which is available in 2/4/8/16-channel width CDR receiver and transmitter arrays, is for ASICs that perform at high bandwidth data communications. The macro meets SONET/SDH OC-48 jitter tolerance mask requirement. The macro
Fujitsu's SFI4-1.0 macro enables the interface of any two chips at an aggregate of 10 to 12.5Gbps in each direction. Sixteen 622/780 Mbps differential data lines (plus one clock) are provided in the transmit direction, and another sixteen (plus one clock)
Fujitsu’s SFI-5 compliant transceiver macro is a 17- channel physical I/O interface macro for ASICs that perform high bandwidth data communication while operating at low power consumption. The transceiver consists of a 17-channel transmitter unit, a 17-ch
To achieve the highest level ofsystem integration, Fujitsu offers avariety ofanalog and mixed-signal macros for customer use inconjunction with its Embedded Arrays and Standard Celllibraries. Data communications, networking, graphics, anddigital audio/vid
ARC is comprised of a Base RISC Engine, the ARC Extension Library, the Architect, integrated test suites, multi-interface architecture, the ARC Co-design toolset, a complete software development toolchain, and both hardware
and software emulators. Provide
The ARM7TDMI embedded CPU core is part of Fujitsu’s IPWare™ Library. The Fujitsu ARM7TDMI processor core, developed by ARM, is implemented in Fujitsu’s 0.25µm process technology. This core contains all of the ARM7TDMI processor features, including a 32-bi
The PCI Synthesizable Core is a part of the Fujitsu IPWare™ Library. The Fujitsu PCI Cores are RTL synthesizable modules that provide an interface between an application and the PCI bus. All PCI protocol and timing requirementsare handled by the core, whi
The CS302 series of 40 nm standard cells is a line of CMOS ASICs that satisfy demands for lower power
consumption, higher speed and higher integration.
These cells offer the minimum level of leakage current in the semiconductor industry, and are able to implement
a mixture of core transistors with three different threshold voltages, as appropriate for the applications
ranging from handheld terminals to digital audiovisual equipment.
The integration level in this series is twice the CS201 series with lower power consumption.
The CS201 series of 65 nm standard cells is a line of CMOS ASICs that satisfy demands for lower power
consumption and higher integration. These cells offer the minimum level of leakage current in the semiconductor
industry, and are able to implement a mixture of core transistors with three different threshold voltages, as
appropriate for the applications ranging from handheld terminals to digital audiovisual equipment.
The integration level in this series is twice the previous series with lower power consumption.
CS101 series, a 90 nm standard cell product, is a CMOS ASIC that satisfies user’s demands for lower power
consumption and higher speed. The leakage current of the transistors is the minimum level in the industry. Three
types of core transistors with a different threshold voltage can be mixed according to user application.
The design rules match industry standards, and a wide range of IP macros are available for use.
As well as providing a maximum of 91 million gates, approximately twice the level of integration achieved in
previous products, the power consumption per gate is also reduced by about half to 2.7 nW. Also, using the highspeed
library increases the speed by a factor of approximately 1.3, with a gate delay time of 12 ps.
The CS91 series 0.11 µm CMOS standard cell is a line of highly integrated CMOS ASICs featuring high speed
and low power consumption. This series incorporates up to 48 million gates which have a gate delay time of 16
ps, resulting in both integration and speed about three times higher than conventional products.
The CS86 series of 0.18 µm standard cells is a line of CMOS ASICs based on higher integration implemented
by introducing wiring pitch reduction technology and on I/O pad placement technology to the conventional CS81
The CS86 series has three types of cell sets (CS86MN, CS86MZ, and CS86ML), covering a variety of applications,
from portable devices requiring low power consumption to image processors requiring large-scale circuitry and
high speed.The three types of cell sets can be contained on one chip, allowing those system LSIs to be implemented
which require low power consumption as well as high-speed operation for certain types of processing.
The CS81 series 0.18 µm CMOS standard cell is a line of highly integrated CMOS ASICs featuring high speed
and low power consumption.
This series incorporates up to 40 million gates which have a gate delay time of 11 ps, resulting in both integration
and speed about three times higher than conventional products.
In addition, CS81 can operate at a power-supply voltage of down to 1.1 V, substantially reducing power consumption.
The CE77 series 0.25 µm CMOS embedded array is a line of highly integrated CMOS ASICs featuring high speed
and low power consumption at the same time.
CE77 series is available in 15 frames with the enhanced lineup of 470 K to 6980 K gates.
While the Penn State Philips (PSP) transistor model is rightly hailed as an excellent alternative to traditional BSIM models for RFIC design, RF designers need to be aware of how PSP models relate to actual device behavior. PSP models do require some judgment on the part of model developers. Equally important is an understanding of the way these models are used in an RF process design kit (PDK).
While CMOS technology has made great strides in its ability to fabricate radio frequency (RF) circuitry, many RF chip designers have yet to take advantage of this capability. After long relying on more expensive technologies such as silicon germanium (SiGe) and gallium arsenide (GaAs), RF designers who transition to the latest RF CMOS processes gain the enormous advantages of full system-on-a-chip (SoC) integration.
This paper describes Fujitsu's CS200/CS200A series 65nm CMOS technology with a focus on the technology's improved performance and low power consumption. These advantages result from the technology's ability to achieve more than twice the density of transistor packing compared to 90nm technology as well as Fujitsu's advanced copper and ultra-low-k material (ULK) technology. The ULK material serves as an inter-level dielectric that reduces parasitic interconnect capacitance compared to previous technologies and thus significantly improves speed and power characteristics. The paper also describes Fujitsu's wide range of packaging choices and rich IP portfolio for use with the CS200/CS200A technology.
This paper discusses Fujitsu's Integrated Device Manufacturing (IDM) service business model. IDM is designed to provide specific services – ranging from flexible design methodologies to a comprehensive set of IPs – as part of development alliances tailored to specific customer needs.
Building on Fujitsu’s expertise in leading-edge CMOS processes and analog design capabilities, the company’s RF CMOS technologies are optimized for wireless networks, cellular communication, WiMAX, digital multi-media broadcast, and navigational applications.
Packaging solutions enable customers to reduce size and space requirements. The packages such as CSP (Chip Size Package or Chip Scale Package) and BGA (Ball Grid Array) support high-density wiring technology and are widely used in the market. Miniaturization has forced the use of new approaches in die packaging in order to achieve the
smallest possible solutions. Fujitsu has launched the mass-production of SON packages -- the world's smallest level. Fujitsu has a mass-production lineup of super compact packages such as FBGA (Fine Pitch BGA) and WL-CSP (Wafer Level CSP) and beyond. The high pin count packages, PBGA( Plastic BGA) and TEBGA (Thermal Enhanced BGA) have been mass-produced in order to fulfill the size and weight limitations, of, for example, portable equipment.
Stacked Multi-Chip Package (Stacked MCP) is one of the most suitable chip scale packages for wireless applications. Its advantage is the compact stacked chip configuration. In the Flash memory and SRAM configuration, the pin layout can accomodate a 128 MB
Wafer bumping services are offered as a preparatory step for flip-chip bonding or as bumping
service alone. The types of solder bumping available include high lead solder, eutectic solder and
lead free solder. Lead free bump, which is composed of tin-silv
Super Chip Scale Package (SCSP) is a wafer level package that is a true chip size package. It provides a potential solution for “known good die?, or one test point operation as compared to two. In single chip packaging, it is customary to have testing at
The size and performance characteristics of Bump Chip Carrier (BCC) package make it well suited for RF devices, wide area networks, and DWDM systems. BCC is a molded, wire-bonded, leadless Chip Scale Package, and has terminals that are thinly plated on to