Fujitsu Microelectronics America, Inc.

New Macros from Fujitsu Microelectronics Deliver Low Power, Low Cost CMOS Performance to 10 Gigabit Ethernet Designs

XAUI-compliant transceiver, 3.125 gig/second parallel CDR transceiver provide highly integrated industry-standard macros in Fujitsu's 0.11 micron CMOS technology

San Jose, CA, September 18, 2002 — Two new macros from Fujitsu Microelectronics America, Inc. (FMA) are ready for application in high-performance ASICs designed for high-bandwidth networking designs including 10 Gigabit Ethernet, WAN routers or switch backplanes. They are also ideal for any backplane line requiring 3.125 Gigabit per second (Gbps) x4 data rates.

Fujitsu's new 802.3 XAUI and 3.125 Gbps transceiver macros provide efficient, industry-standard I/O capabilities that combine with the company's leading-edge process technology to simplify the system design process and reduce time to market. Both macros are available as a library cell for ASIC designs.

XAUI Macro Meets IEEE 802.3ae Specifications
The new XAUI macro meets all IEEE 802.3ae specifications including jitter generation under 0.35UI without pre-emphasis and jitter tolerance of more than 0.60UI, peak-to-peak total. The macro also matches the 802.3 sinusoidal jitter-tolerance mask requirement. The 3.125Gbps x 4 channel unidirectional data transfer rate for 10G Ethernet complies with the IEEE 802.3ae XAUI definitions for linking physical-layer devices with upper-layer devices.

"The integration of the XAUI macro into an ASIC device reduces line-card footprint and power as opposed to using discrete XAUI interface chips," said Yuk Yung, director of marketing at Fujitsu Microelectronics America. "Our strength is in developing high-performance, leading-edge ASICs with embedded high-speed interconnect technology." (See the company's announcement dated September 18, "Fujitsu Named #2 ASIC Supplier Worldwide by iSuppli.")

The XAUI macro provides a 156MHz input reference clock and parallel interface along with 4-channel CDR Rx and 4-channel Tx arrays, an AC-coupled differential interface, and differential PCML at 1.2V and 1.8V. The macro also incorporates 1:16 serialization-deserialization (SERDES) with 16:20 gearbox, 8B/10B coding and lane alignment provided as an RTL/netlist. Pre-emphasis-based Tx equalization allows up to 12dB high frequency loss.

Parallel Transceiver Meets SONET/SDH OC-48 Jitter Tolerance
The 3.125 Gbps parallel transceiver is a selectable 2/4/8/16-channel CDR receiver and transmitter array that meets all SONET/SDH OC-48 jitter tolerance requirements. The macro provides a 1:16 SERDES capability, with an input reference clock of 156 MHz to 195 MHz and parallel interface. Programmable data rates include 622 Megabits/second to 780 Mbps, 1.25 Gbps to 1.56 Gbps, and 2.5 Gbps to 3.125 Gbps.

Both new macros feature 100mW/ch power dissipation. Each includes bias circuit and PLL, maximum pre-emphasis, integrated 50-ohm termination resistors, and independent dual-loop PLL-based CDR on each Rx channel. Power requirements are 1.2V+/-0.10V and/or 2.5V+/-0.20. Junction temperature is 0C to 125C.

"Fujitsu's value-added XAUI transceiver macro and parallel transceiver macro enable users to create a variety of complex ASIC designs for networking and storage applications," said Keith Horn, Vice President of Marketing at FMA. "These new products deliver the low cost and low power required for the new generation of 10 Gigabits per second Ethernet networking applications."

The Fujitsu application engineering team works closely with customers to identify specific IP requirements. Fujitsu then provides the user with a Verilog model, including front-end simulation and C model, a complete Library Exchange Format (LEF) with floorplanning and place/route data; and Design Compiler Model to support the 3.125Gbps x4 XAUI Transceiver macros.

The two new macros are the latest in Fujitsu's industry-leading selection of IP for networking and storage applications. Last June the company introduced SERDES Framer Interface SFI-5 and SFI-4 macros for system-on-chip (SoC) ASICs in gigabit and terabit routers, optical cross connect switches and Dense Wave Division Multiplexing (DWDM) optical transmission systems.

---

About Fujitsu Microelectronics America

Fujitsu Microelectronics America, Inc. designs, markets and supports a broad range of semiconductors and electronic devices. Fujitsu is a leading edge ASIC supplier and holds the number two position in the ASIC market according to iSuppli, a market research firm.

For product information, call 1-800-866-8608 or visit the company's web site at http://www.fma.fujitsu.com/asic

---

Press Contacts