Fujitsu Microelectronics America, Inc.

Fujitsu Microelectronics' High-Density Digital Chips Lead Success of TRW's Astrolink Payload

Triple-mode input/output data-transfer capability, low power provide optimal IP for next-generation network systems

San Jose, CA, May 22, 2001 — Fujitsu Microelectronics, Inc. (FMI) today announced a new triple-mode physical I/O transceiver interface macro for use in complex system-on-chip (SOC) ASIC designs for high-end networking applications. The new macro provides data transfer rates of 2.5 Gbps, 1.25 Gbps and 622 Mbps, which can be selected based on system requirements. It has been developed specifically for products like add-drop multiplexers, broadband cross-connects, fiber optic terminators and test equipment, and systems equipment built using Wavelength Division Multiplexing (WDM).

The new parallel transceiver macro, which is available as a core library cell for ASIC design, provides a 16-bit transmitter and 16-bit receiver array. Each receiver bit includes a Clock Data Recovery (CDR) with analog and digital phase locked loop. The receiver also includes an integrated line equalization capability, which compensates for inter-symbol interferences, and equalizes losses up to 12 dB. The macro incorporates an on-chip 50 ohm termination resistor for receiver and transmitter, along with PRBS generators and a comparator, for easy testing. Power dissipation at operating speeds of 2.5 Gbps is less than 2.5W for the 16-bit transmitter block and the 16-bit receiver block. The input reference clock operates at 156 MHz.

Customers can also select from a variety of other channel sizes depending on their specific applications, power consumption and space requirements.

"This new macro is a critical piece of IP for a broad range of our networking and communications equipment customers who can use it for their next-generation high-bandwidth systems," said Shigeru Fujii, senior vice president of FMI's Systems Solutions Group. "Making this macro part of the ASIC IP library lets us provide high-end ASIC solutions at a very competitive price. We have a number of strategic engagements with customers who will be able to use this macro as a key differentiator in their high-end ASIC designs," he added.

The new macro, which can operate on either 1.8V or 3.3V, is fabricated using Fujitsu's 0.18-micron CMOS technology. It is available in a wide range of Enhanced Ball Grid Array (EBGA) and Flip Chip BGA (FCBGA) packages. Fujitsu supports the new networking macro with Verilog models, front-end simulation, C model with Verilog wrapper and a complete Library Exchange Format.

Click here to download fact sheet
2.5G High-speed I/O

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About Fujitsu Microelectronics America, Inc.

Fujitsu Microelectronics, Inc. (FMI) designs, markets and manufactures a comprehensive portfolio of advanced semiconductor and electronic devices. For product information, call 1-800-866-8608 or visit the web site at http://www.fmi.fujitsu.com/asic/Main01.asp.

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