Publication Topic: Deep Submicron Effects

a) Performance Optimized Layout

• T. Shibuya, R. Murgai, T. Konno, K. Emi, and K. Kawamura, "PDL: A New Physical Synthesis Methodology," In the Proceedings of ISQED 2003 (Invited paper).
• S. Chakraborty and R. Murgai, "Layout-driven Timing Optimization by Generalized DeMorgan Transform," In the Proceedings of VLSI Design, India, 2002. Also, in the Proceedings of IWLS 2001.
• R. Carragher, R. Murgai, S. Chakraborty, Y. Kanazawa, T. Shibuya, M. Prasad, A. Srivastava, N. Vemuri, and H. Yoshida, "Layout-driven Logic Optimization," In the Proceedings of DATE, 2001 Designers' Forum, Munich, Germany. Also, in the Proceedings of IWLS 2000.
• R. Murgai, "Layout-driven Area-constrained Timing Optimization by Net Buffering," In the Proceedings of the International Conference on Computer-Aided Design, 2000. Also, in the Proceedings of IWLS 2000.
• R. Murgai, "On the Global Fanout Optimization Problem," In the Proceedings of the International Conference on Computer-Aided Design, 1999. Also, in the Proceedings of IWLS 1999.
• R. Murgai, "Performance Optimization Under Rise and Fall Parameters," In the Proceedings of the International Conference on Computer-Aided Design, 1999. Also, in the Proceedings of IWLS 1999.
• R. Murgai, "Delay-constrained Area Recovery via Layout-driven Buffer Optimization," In the Proceedings of VLSI Design, India, 2000. Also, in the Proceedings of IWLS 1999.
• R. Murgai, "On The Complexity of Minimum-delay Gate Resizing Under Load-dependent Delay Model," In the Proceedings of IWLS 1999.
• A. Oliveira and R. Murgai, "An Exact Gate Assignment Algorithm for Tree Circuits Under Rise and Fall Delays," In the Proceedings of the International Conference on Computer-Aided Design, 2000. Also in the IEEE Transactions on Computer-Aided Design, June 2003. Also, in the Proceedings of IWLS 2000.
• S. Chakraborty and R. Murgai, "Complexity of Minimum-delay Gate Resizing," In the Proceedings of VLSI Design, India, 2001.
• R. Murgai, "Efficient Global Fanout Optimization Algorithms," In the Proceedings of ASP-DAC, 2001 (Nominated for the Best Paper Award).
• R. Murgai, "Net Buffering in the Presence of Multiple Timing Views," Published in the Proceedings of VLSI Design January, 2004, Mumbai, India. Also, in the Proceedings of IWLS 2002.
• R. Murgai, "Improved Layout-driven Area-constrained Timing Optimization by Net Buffering," In the Proceedings of VLSI Design, India 2005.

b) Crosstalk and Substrate Noise Analysis

• Z. Wang, R. Murgai, J. S. Roychowdhury, "Automated, Accurate Macromodelling of Digital Aggressors for Power/Ground/Substrate Noise Prediction," in the Proceedings of DATE 2004. A detailed version appeared in IEEE Transactions on CAD, January 2005.
• Y. Li, R. Murgai, T. Miyoshi, A. Verma, "XTalkDelay: A Crosstalk-Aware Timing Analysis Tool for Chip-Level Designs," In the Proceedings of ICCD 2004.
• R. Murgai, S. Reddy, T. Miyoshi, M. Tahoori, T. Horie, "Sensitivity-based Modeling and Methodology for Full-chip Substrate Noise Analysis," in the Proceedings of DATE 2004.

c) Advanced Clock Distribution

• No Publication Available.