M-Y Ko, P. K. Murthy, S. S. Bhattacharya, "Compact Procedural Implementation in DSP Software Synthesis through Recursive
Graph Decomposition," 8th International Workshop on Software and Compilers for Embedded Systems (SCOPES), Amsterdam, Netherlands,
September 2004, (best paper award finalist).
P. K. Murthy, S. S. Bhattacharyya, "Buffer Merging: A Powerful Technique for Reducing Memory Requirements of Synchronous
Dataflow Specifications," ACM Transactions on Design Automation of Electronic Systems, vol. 9, no. 2, pp. 212-237, April
2004.
S. S. Bhattacharyya, P. K. Murthy, "The CBP Parameter-A Module Characterization Approach for DSP Software Optimization,"
Kluwer Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology, vol. 38, no. 2, pp. 131-146, September
2004.
P. K. Murthy, E. A. Lee, "Multidimensional Synchronous Dataflow," IEEE Transactions on Signal Processing, vol. 50, no.
8, pp. 2064-2079, August 2002.
Evgueni Goldberg, Mukul R. Prasad and Robert K. Brayton, "Using Problem Symmetry in Search Based Satisfiability Algorithms,"
in Proceedings of the Design Automation and Test in Europe (DATE 2002), March 2002. (Best Paper Award)
E. M. Clarke, M. Fujita, S. P. Rajan, T. Reps, S. Shankar and T. Teitelbaum, "Program Slicing for VHDL", International
Journal on Software Tools for Technology Transfer (STTT), Volume 4 (1): 125-137, 2002.
S. O. Memik, F. Fallah, "Accelerated Boolean Satisfiability for Scheduling Control/Data Flow Graphs," International Conference
on Computer Design (ICCD), Freiburg, Germany, Sept. 2002.
S. O. Memik, F. Fallah, "Accelerated Boolean Satisfiability-Based Scheduling for High-Level Synthesis," International
Workshop on Logic and Synthesis (IWLS), New Orleans, June 2002.
S. Rajagopalan, S. P. Rajan, K. Takayama, S. Rigo, and G. Araujo, "A Re-targetable VLIW Compiler Framework for DSPs with
Instruction Level Parallelism", IEEE Transactions on Computer-Aided Design, Volume 20, Number 11, November 2001, pages
1319-1328.
I. Ghosh, S. Ravi, N.K. Jha and V. Boppana, " Fault-Diagnosis-Based technique for establishing RTL and gate-Level correspondences,"
in IEEE Transactions on CAD, Dec. 2001. Also in Proc. IEEE International Conference on Computer Design, Austin, Texas, Sept.
2000.
V. Boppana, I. Ghosh, R. Mukherjee, J. Jain, and M. Fujita "Hierarchical diagnosis targeting RTL circuits," in Proc. International
Conference on VLSI Design, Calcutta, India, Jan. 2000.
I. Ghosh, N.K. Jha and S. Bhawmik, "A BIST scheme for RTL controller/data paths based on symbolic testability analysis,"
in IEEE Transactions on CAD, Jan. 2000.
I. Ghosh, S. Dey and N.K. Jha, "A fast and low cost testing technique for core-based system chips," in IEEE Transactions
on CAD., Aug. 2000.
S.P. Rajan, M. Fujita, Ashok Sudarsanam, and Sharad Malik, "Development of an Optimizing Compiler for Fujitsu Fixed Point
DSP", Proceedings of the International Workshop in Hardware/Software Codesign (CODES'99), May 1999, Rome, Italy.
I. Ghosh, A. Raghunathan and N.K. Jha, "Hierarchical test generation and design for testability for ASPPs and ASIPs,"
in IEEE Transactions on CAD, Mar. 1999.
I. Ghosh, N.K. Jha and S. Dey, "A low overhead design for testability and test generation technique for core-based systems,"
in IEEE Transactions on CAD, Nov. 1999.
R. Murgai and M. Fujita, "On Minimizing Transitions by Data Modifications," In the Proceedings of the DATE, Munich, 1999.
R. Murgai, J. Jain, and M. Fujita,"Efficient Scheduling Techniques for ROBDD Construction," In the Proceedings of VLSI
Design, Goa, India, 1999.
R. Murgai, F. Hirose, and M. Fujita, "Speeding Up Look-up Table Driven Logic Simulation," In the Proceedings of VLSI Design,
Portugal, 1999.
I. Ghosh, S. Ravi, R. Roy and S. Dey, "Controller re-synthesis for testability enhancements in RTL controller/data paths,"
in Journal of Electronic Testing: Theory and Applications (JETTA), Oct. 1998.
I. Ghosh, N.K. Jha, "High level test synthesis: A survey," in Integration, the VLSI Journal, Dec. 1998.
R. Murgai, M. Fujita, and A. Oliveira, "Using Complementation and Resequencing to Minimize Transitions," In the Proceedings
of the Design Automation Conference, 1998.
R. Aggarwal, R. Murgai, and M. Fujita, "Using Network Partitioning to Speed Up Technology-independent Timing Optimization,"
In the Proceedings of the International Conference on Computer-Aided Design, 1997. Also, in the Proceedings of IWLS 1997.
R. Murgai and M. Fujita, "Delay Estimation and Optimization of Logic Circuits: A Survey," In the Proceedings of the Asia-Pacific
Design Automation Conference, Japan, 1997.
R. Murgai and M. Fujita, "Some Recent Advances in Software and Hardware Logic Simulation," In the Proceedings of the VLSI
Design, India, 1997.
R. Murgai, S. Krishnan, and M. Fujita, "Data Sequencing for Minimum-transition Transmission," In the Proceedings of IWLS
1995. Also, in the Proceedings of the VLSI '97, Gramado, Brazil. Nominated for the Best Paper Award.
R. Murgai, F. Hirose, and M. Fujita, "Logic Synthesis for a Single Large Look-up Table," In the Proceedings of the International
Conference on Computer Design, 1995. Also, in the Proceedings of IWLS, 1995.
