LSI Technology

Fujitsu Laboratories LSI Technology Research focuses on advanced circuit and semiconductor technologies for high-speed and low power computing and communications. We are currently actively involved in the following areas:

• Advancement of the state-of-the-art in logic and memory circuits for high performance microprocessors.
• Transmission of information through electrical and optical channels with high-bandwidth and low-latency, focusing on the physical layer.
• Development of circuit and architectural techniques to reduce power consumption in future highly integrated systems-on-a-chip.
• Testability of embedded logic and memory.

In the pursuit of our goals, we have at our disposal the full resources of Fujitsu Laboratories of America and Fujitsu Laboratories Ltd. in Japan, as well as access to the advanced semiconductor processes developed by Fujitsu and its partners. We also have an active program to sponsor basic research at Universities.

Research Themes

1. High-speed Low-power Datapath Design

Using high-performance CMOS silicon-on-insulator (SOI) technology, we have been investigating novel arithmetic unit designs that achieve high-speed using half the power of conventional CMOS implementations. These designs exploit the intrinsic speed benefits that accrue from the floating-body in SOI, and in addition conserve power by recycling charge, rather than computing using the traditional precharge-discharge method of dynamic circuits.

2. Multi-port Memories

Multi-port memories, the most important example of which is a register file, are a critical path in most processor designs. Moreover, due to their increasing size and high switching activity in recent superscalar and VLIW designs, they account for a significant proportion of the power consumption.

Testing of multi-port memories has traditionally been done using scan, which is effectively a low-speed or DC test capable of detecting stuck-at faults, but weak at detecting signal integrity faults. Recent designs have many opportunities for untestable signal integrity faults due to extensive coupling between ports, compounded by the relentless scaling of CMOS technology. Technology scaling contributes to signal integrity problems by increasing wiring resistance and coupling capacitance.

Our research is aimed at using the most advanced circuit techniques to achieve very high speed necessary for the competitiveness of future processors, while at the same time exploiting the architectural features of a design to configure circuits to minimize switching activity and, therefore, power consumption.

In addition, we are developing ultra-compact built-in-self-test (BIST) circuits that use the ubiquitous on-chip PLL to test memories at-speed during wafer-probe, and that go far beyond the traditional stuck-at fault testing. We envision that future IP memory cores will be delivered with the test problem solved within the core, greatly simplifying the job of integration into a larger SOC design.

3. High-speed Communications

The insatiable demand for bandwidth created by the commercialization of the Internet has resulted in staggering growth in the optical transport market. As a leader in this market, Fujitsu is committed to advanced research to maintain its competitive edge.

Concurrently, in advanced multiprocessor and SOC designs, transmitting data through a system and even across a large die is becoming a serious design challenge due to increasing clock speeds, larger die sizes relative to the circuit density, and scaling-induced degradation of wiring bandwidth and signal integrity. As a result of these technology trends, the ratio of power contributed by the wiring to power consumed in actual computation is increasing with each generation of technology.

At FLA, we are using advanced CMOS and bipolar technologies to address both of these challenges. In the high-speed optical transport arena, we are active in exploring design methodologies and circuits needed for future high-speed SONET/SDH transceivers. Due to stringent speed and jitter specifications, the technology required goes beyond what is available using traditional CMOS. At the same time, the desire to reduce cost and power and improve integration by avoidance of exotic III-IV compound semiconductor technology is pushing us toward finding solutions using silicon. In the on-chip communications arena, we are investigating, architectural, device technology, and circuit solutions to improve latency, bandwidth, and reduce power consumption.