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Technology

Through the technology and services we provide, together with our customers, we are contributing to the realization of the coming smart society. Through our excellent technology and our support, we realize products that support a smart society.

Ultra-Low Power Technology

In order to achieve the ultra-low power consumption that is necessary for mobile and wearable devices, we developed the "C55DDC" technology. "C55DDC" is a technology having transistors that can operate at ultra-low voltage and ultra-low leak transistors. These transistors adopt a structure that is different from conventional CMOS in order to achieve ultra-low power consumption. 

As a result, the "C55DDC" achieves a reduction in power consumption of approximately 50% at the same operating speed when compared to the "C55LP". Furthermore the leakage current of the ultra-low leak transistors has been decreased to pico-ampere levels, and even to femto-ampere levels. With the "C55DDC," we provide low power solutions meet the needs of our customers' various needs. 

Our company is the first in the world to manufacture these ultra-low voltage and ultra-low leak transistors, and we are the only foundry mass-producing such products.

DDC in detail

In addition to standard CMOS technologies MIFS is offering the Deeply Depleted Channel (DDC) technology for 55 and 40nm which can be shortly summarized as: 

DDC = FD-SOI features @ 55nm/40nm wafer cost 

In more detail the DDC advantages can be described as follows:

  1. Similar to SD-SOI technologies the variation of transistor parameters in a DDC process across a device or wafer is smaller compared to bulk technologies. As a result the spread of path delays becomes smaller and easier to handle. 
  2. In contrast to standard technologies and similar to FD-SOI, DDC has a higher sensitivity for back bias voltages. This higher sensitivity opens different options to either dynamically or statically modulate the device performance. This is a major advantage when designing ultra low power devices. 
  3. Finally on-chip memories implemented in DDC technology have significant advantages at low supply voltages. More precise, DDC offers a stable SRAM operation in near or sub threshold regions.

The power voltage needs to be lowered in order to reduce the power consumption of the CMOS circuit. Previously, power voltage was lowered by reducing transistor size. However, since the 90nm process, the variations of threshold voltages resulted from the transistor's dopant fluctuations had been making it difficult for power voltage to be lowered by reduction in transistor size.

DDC transistor structureDiagram1: DDC transistor structure

The C55DDC transistor structure is shown in Diagram 1. For the channel part of the planer CMOS structure, dopant fluctuations can be reduced by creating multiple layers with different impurity concentrations. This resulted in the reduction of power consumption achieved by lower power voltage. A DDC transistor (Diagram 1) contains layers of different dopant concentrations at the channel region. 

This structure helps reduce the fluctuation in the dopant distribution, which is a major cause of the threshold voltage variation, thus enables the lower supply voltage. Since the transistor is built on the conventional planar CMOS structure, it can be manufactured with the conventional semiconductor fabrication equipment. There is also another advantage of having the conventional CMOS structure, that circuit developers can reuse the existing design resources. 

Fujitsu Semiconductor has developed CS250S, a combination of the 55nm process in Mie Plant and the DDC, and successfully implemented the DDC technology into production for the first time in the world. In addition to reducing the dopant fluctuation by DDC, Adaptive Body Bias (ABB) control, which compensates the other process-induced variations by applying an optimum body bias for each die, CS250S has achieved the 50% lower active power compared with the conventional technology, while maintaining the same operation speed. 

Plugin Flash 

Furthermore MIFS is adding a plugin Flash option to the DDC processes. Plugin Flash comes with two advantages. Beside lower cost this option also provides lower power compared with conventional embedded Flash technologies. Due to the high number of designs for industrial and automotive applications MIFS has been producing so far, MIFS is prepared to support customers on their effort for a respective qualification of their final devices. 

Nonvolatile memories

Nonvolatile memories are embedded in a variety of electrical equipment such as automobiles, IC cards, smart meters, etc. We mount nonvolatile memories with high CMOS compatibility our customers' products at the lowest cost. 

RF

Wireless communication is a key word in the rapidly progressing IoT society. Our ULP/LP technology comes with PDK and the devices necessary for RF design (such as varactors, inductors, and MOM/MIM capacitors), allowing us to provide optimal RF solutions to our customers. MIFS process overview

MIFS process overview MIFS Process overview