Reliability of UltraSPARC T1 Processor
UltraSPARC T1 processors have high-level RAS functions (Reliability, Availability, Serviceability). Data in level1 cache memory is protected by parity check and level2 cache memory and registers by ECC.
If an uncorrectable error occurs in level1 cache memory, the processor downgrades by core unit. Data in registers is protected by ECC.
SPARC Enterprise entry models using UltraSPARC T1 provide highly reliable systems.
| Error detection | Error correction | Downgrade capability | |
|---|---|---|---|
| Level1 cache memory | Parity | Retry | Dynamic core downgrade |
| Level2 cache Memory | ECC | ECC | - |
| Register | ECC | ECC | Dynamic core downgrade |
Advanced RAS functions improve business continuity
Data protection mechanisms in cache memory
As cache memory suffers from more intermittent failures (*1) than all other processor circuits; cache memory data protection mechanisms are required to prevent server down or performance slow-down.
UltraSPARC T1 level1 cache is protected by parity check and level2 cache by ECC. If a one-bit error occurs in level1 cache, data is directly re-read from level2 cache and processed again. If an uncorrectable error occurs in level1 cache, the faulty core is downgraded and the remaining cores maintain system operation.
So even if an error occurs the system keeps on running correctly.
*1: Intermittent errors occur at random points causing data error. Referred to as “soft errors” they are caused by radiation, magnetic interference and heat.
Register data protection
Registers in UltraSPARC T1 CPU consist of SRAM, the same type of RAM used for cache memory. One-bit errors occur relatively frequently in SRAM, registers are protected by ECC.
Cache scrubber
Cache scrubber is a hardware function that checks for errors in level2 cache memory. If a one-bit error occurs, the error is recovered.
