Explanations

• Check circuit
  Checks calculation results. If an error is found, the circuit automatic performs a recalculation.
• Parity check
  Detects one bit data errors using a parity bit added to data.
• Memory protect
  Prevents specific memory space from being overwritten.
• Memory protection key
  Protects executing programs from corruption by placing memory protection keys on each memory block.
• System surveillance equipment/Service processor
  Independent (of main processors) system management.
• Instruction retry
  Process to automatically recover from instruction errors.
• ECC
  Corrects one bit errors and detects two bit errors by checking ECC codes.
• Log out control
  Records internal status of CPUs in error.
• Memory switching
  Isolates failed memory blocks and reboots with a downgraded system.
• History
  A dedicated circuit that records all internal CPU status.
• Memory patrol
  Mechanism for intermittent memory error recovery by reading memory regularly and correcting one bit errors.
• Chip switching and automatic allotment
  Automatic alternation of chip used.
• Extended ECC
  Protects memory data from memory chip failure Automatic power control Turns on /off system and air conditioning power at specified times.
• Hot replacement
  Replaces failed components while system remains operational.
• Battery backup
  Use of an additional battery to protect system from data corruption due to abrupt power-downs.
• Pipeline
  Parallel instruction execution, using assembly line style execution steps.
• Prioritized processing
  Enables processes with higher priority to interrupt lower priority processes.
• Variable length word processing
  Handles instruction data of variable lengths for more efficient use of limited memory space.
• Building block
  Expands system flexibly by combining multiple blocks.
• Dynamic relocation
  Allocates new memory addresses by transforming memory in use.
• Software paging
  Enables the saving of memory data to a storage device as virtual memory.
• Memory interleaving
  Improves memory access performance by accessing different memory locations in parallel.
• Buffer memory
  Intermediate area between CPU and memory (currently referred to as cache memory)
• Look-ahead control
  Executes only the fetch cycle for instructions in advance. After relevant instruction is determined, the instruction is fetched.
• Triple-layered memory
  Enables the storing of data and instructions in Level1/Level2 cache/main memory based on access frequency.
• High speed branching
  Enables swift instruction fetching by calculating instruction address after branching and fetching instruction.
• Branch prediction
  Predicts instructions after conditional branching.
• Harvard Architecture
  Cache memory that includes instruction and data components.
• Pre-fetch
  Preliminary read of memory data to cache memory based on identifying memory with high probability based on cache access regularity.
• Branch history
  A logical circuit that records past branching for the purpose of branch prediction.
• Store in
  A memory writing method where data is written to cache memory and is reflected in main memory afterwards.
• Super scalar
  Enables execution of instructions in parallel.
• Out of order
  An instruction execution mechanism that executes instructions ready to be executed, regardless of instruction order.
• Non blocking cache
  Shrinks memory access time by accessing cache memory while executing other instructions without cache memory access.
• One Point Copy
  Multiple, point-in-time copies of production data which effectively complete in seconds, providing faster data backup and recovery.
• Equivalent Copy
  Remote synchronous and asynchronous file mirroring options for business continuity protection
• Cyclic CM function
  Method of maintaining cache redundancy in multi-controller storage systems, even if a controller fails.