Design of low power consumption LSIs

Technologies for low power consumption
To meet the customers' demands for low power consumption, we are engaged in various efforts and approaches. The combination of various technologies effectively enables to design low power consumption LSIs.

Technologies for low power consumption

Design techniques supporting multiple power supplies and power gating
CPF Support | UPF Support

Low-power Design Technology
Clock Gating | Multiple power supply design | Multi-Vth design | Power gating

Design techniques supporting multiple power supplies and power gating

Fig.1 Design Flow

CPF Support

In our RDF V3.0, the physical design of multiple power supply design and power gating has been facilitated dramatically by supporting the standard power supply description format CPF ahead of others in the industry.

In addition, highly reliable design can be realized by sharing the single power format CPF with the entire flow, since CPF is described and verified by the logic designer as a GOLDEN information.

Fig.1 presents the overall design flow. Although the over view of the flow is the same, a new function has been added to each step. For example, an appropriate delay calculation is executed to suit the voltage for each power supply area (Power Domain) in logic synthesis, layout, and sign-off verification. Automatic placement clock tree generation, and timing optimization are executed in the layout with consideration given to the physical areas of the Power Domain while the level shifter (LS), isolator (ISO), and power shutdown switch (PSW) are also automatically inserted. The proper insertion of these level shifters, isolators, and power switches is checked by the newly introduced lowpower checker, "Conformal-LP." The IR Drop analysis and LVS verification including the PSWs, LSs and ISOs are also supported in RDF V3.0 flow.

UPF Support

Fujitsu Microelectronics supports the customers who design using the UPF.

Low-power Design Technology

Clock Gating

Clock gating is a conventional technology in which the operating power consumption is reduced by partially stopping clock supply to the resister when it is known beforehand that the input of the register (FlipFlop) will not transition (local clock gating) or by stopping clock supply to suspended blocks (global clock gating).

Fig.2 Clock gating

Multiple power supply design

Multiple power supply design can be used to reduce operating power consumption and standby power consumption (leak current) by supplying multiple power supplies with different voltage levels and supplying low power supply voltage to blocks with low operation frequencies. Areas with different voltages must be designed physically separate from one another and a cell called a level shifter must be inserted to enable the interface signals between them to convert the signal level.

Fig.3 Multiple power supply design

Multi-Vth design

Fig.4 Multi-Vth design

Multi-Vth design is another conventional technology in which the leak current is optimized while satisfying the timing constraint by efficiently using the standard cells consisting of transistors with high speed and relatively large leak current in paths with critical timings and the standard cells consisting of transistors with low speed but small leak current in non-critical paths.

Power gating

Power gating is a technology that has been gaining popularity in recent years. It dramatically reduces the leak current by shutting off the power supply to suspended blocks. The method which has switches to shut down the power supply in an LSI is called "on-chip power gating" (Fig.5).

Similar to multiple power supply design, the block to shut down the power supply is designed physically separate from others. In addition, since signals from a block with power supply shutdown may be in neutral state that is not high or low, these signals as they are must not be received by operating circuits. A circuit called an isolator must be inserted for such an interface (Fig.6).

Caution is also required in logic verification. Since the conventional logic simulator cannot handle the status of power supply shutdown, a risk exists that a bug is not found in which the power supply is not actually supplied to a circuit that appears to be operating on logic simulation (Fig.7).

Furthermore, the power supply noise generated when the power supply shutdown switch turns ON needs to be suppressed to a level that does not affect other circuits when adopting on-chip power gating (Fig.8).