Leading-edge 45-nanometer LSI technology

State-of-the-Art of 45 nm and 40 nm

The most advanced CMOS technology requires not only finest gate definition technique but also new techniques of high-speed interconnects, and stressors, shallow-junctions.
Since 65-nm node, Fujitsu has adopted silicon-nitride films as Dual Stress Liner (DSL) to enhance drive-ability of MOS transistors. The technique was refined and another new technique was employed to introduce higher stress into channels of 45- and 40-nm transistors.
CMOS transistor manufacturing process contains annealing to activate impurities. Fujitsu uses Mili-Second Annealing technique to form extremely shallow junctions for high-performance of 45- and 40-nm transistors. A wafer is heated up to about 1000 degrees Celsius during few thousandth second. The technique enables to minimize dopant diffusions in the silicon substrate and to lower resistances of source and drain of the transistors at the same time. Fujitsu is leading the world for the technique.
In addition to high-performance technology with 45-nm design rules, cost competitive 40-nm technology is being released shortly. The 40-nm technology provides low-leakage transistors and achieves 80% chip area shrinkage comparing to 45-nm.

Copper Interconnect and Low-k Inter-level Dielectric

Fujitsu developed copper interconnect technology in the early stages and has been utilizing it for CMOS products since 180-nm node. Fujitsu continues to refine the manufacturing technology by aggressively pursuing high-performance and high-reliability even after the establishment. For 45-nm node, nano-clustering silica (NCS) films are employed, which have a lower dielectric constant than a conventional SiOC film. The technique enables ultra high-speed operations of circuits.