ZIPC

ZIPC is a CASE tool that supports software development in the midstream stage using "Extended-Hierarchy State-Transition-Matrix Design Method Version 2.0."
By using the state-transition matrix, it enables the creation of designs with no missing data. Because ZIPC is equipped with functions for editing the state-transition matrix, for debugging OSEK, ITRON(REALOS), and others in the design stage, and for automatically generating C-source code, it contributes to the improvement of software quality and reduction of development man-hours.
It uses a converter for linkage to upstream Statemate MAGNUM, and uses state-transition animation and break-point setting during C-source generation and debugging for connection to downstream SOFTUNE.

Development process based on ZIPC and SOFTUNE connection

When a state-transition chart of Statemate MAGNUM is convered to a state-transition matrix of ZIPC, missing data is clearly indicated, allowing the specifications for those sections to be set and added easily.
The information required by the microcontrollers, such as timers, I/O ports, and interrupt vectors, is described in the ZIPC document.
Upon completion of design using the state-transition matrix, ZIPC VIP is used to conduct a state-transition-matrix simulation in order to verify the logic.
Upon completion of the logic verification, C code is generated by ZIPC.
The generated C-source file is automatically registered as a SOFTUNE project.
From this stage, SOFTUNE's simulator and ZIPC VIP are linked for operation verification, or ICE is used to test a packaged product using actual equipment.