Even if master transmission (start condition generation instruction) is executed, a transfer end interrupt (INT bit=1) does
not occur.
Answer : The I2C bus level may be SCL=L and SDA=L. If the start condition generation instruction is executed in this status, a transfer
end interrupt (INT bit=1) does not occur because the master cannot output a clock. Once this status occurs, the BB bit is
set to "0" and the AL bit is set to "1." Detect this status with the BB and AL bits to disable I2C and release the
status.
After a start condition had occurred during master transmission execution, a communication error occurred because the slave
(communication destination) drove the SDA line at a low level. Despite this fact, the master continuously outputs clocks.
Answer : After a master condition has occurred during master transmission execution, I2C mounted on an FMC family always outputs nine
clocks when SCL is free. After nine clocks have been output, an INT bit interrupt flag occurs to cause the interrupt. It is
necessary to confirm each flag in this interrupt routine. Immediately after a bus error has occurred, a bus error interrupt
occurs and I2C is automatically disabled with hardware.
At power-on, is there any problem in supplying 5 V to the I2C bus port prior to the power supply for the microcomputer? (Target:
MB91150series)
Answer : The port of the I2C bus is an N-ch open drain pin, of which output power voltage is determined by the Vss standard. Therefore,
there is no problem in supplying 5 V to the I2C bus port prior to the power supply for the microcomputer.
Is the trigger by STGR[bit] of the control status register (PCN) unrelated to the setting of general control register 1 (GCN1)?
Answer : It is possible to select the trigger input by GCN1 for triggering. Alternatively, the software trigger bit of the control
status register (PCN) can trigger. They have a relationship in which either the trigger selected by GCN or the software trigger
is selected.
The SEG wave and COM wave are not in synchronization when the value of display RAM was changed during LCD display. Why?
Answer : When the display RAM is rewritten, the SEG display is changed immediately, so it is not in synchronization with the COM signal.
When the display RAM is not changed, switching of the SEG wave is in synchronization with that of COM wave.
