Does the sub-clock stop when the PLL2EN bit of the clock source control register (CLKR) = 0: sub-clock selection prohibited
is specified?
Answer : The PLL2EN bit of the clock source control register (CLKR) specifies whether to prohibit the transfer to sub-clock and does
not stop the sub-clock itself.
How many cycles is the PLL stabilization wait time? (Target: MB91350A series/ MB91150 series)
Answer : For operation with quadruple of 12.5 MHz (internally 50 MHz), the specification of Look Up Time of mounted macros is about
300 us. 328 us is recommended for chips. MB91150 series: It is necessary to take the stability waiting time of 300us or more.
When the multiplication ratio of PLL is changed, how long is the locking wait time? Changing multiplication during PLL operation
is ever possible? (Target: MB91350A series)
Answer : When the multiplication ratio is changed during PLL use, it automatically transfer to the oscillation stabilization wait status
for ensuring the PLL locking time after changing the setting. Therefore, the oscillation stabilization wait time specified
in the standby control register becomes the locking wait time. For the operation, the program operation stops during the stabilization
wait time.
The initial value of VSTP is the PLL oscillation. Is there any problem in using PLL immediately after the oscillation stabilization
wait time? Or, waiting for a given length of time is required?
Answer : Because the PLL activation starts after power-on reset , PLL operates stably after the oscillation stabilization wait time.
Is it better to switch the PLL settings gradually?
Answer : We recommend to switch all the clocks (the internal bus clock, external bus clock, and peripheral system clock) from the lower
frequency to the target clock not suddenly but gradually for suppressing the internal voltage effect and surge.
When applying 24 MHz as the source oscillation input to FR, the same frequency is to be used for the internal PLL because
doubled frequency would exceed the operable frequency. In this case, 24-MHz clock is to be input to the built-in peripheral
devices. Is this usage possible? (Target: MB91F127)
Answer : Both CPU-system and peripheral-system are operable at 25-MHz or less operating frequency. Therefore, 24-MHz clocks can be
supplied to peripheral devices.
There is no pin for confirming the CPU-system operating frequency. How can we confirm it? (Target: MB91101)
Answer : Confirm the CPU-system operating frequency by checking the CLK pin outputting the same clock as the external bus frequency
and ON/OFF of the clock doubler bit of GCR.
Answer : Generating low pass filter with the load capacitor to reduce the higher-pass gain can suppress the abnormal oscillation of
high frequency wave. Additionally, it limits the gain to IC to improve the matching between the IC and oscillator, so that
unnecessary ringing is reduced and overshoot or undershoot is suppressed. For details, contact the supplier of the oscillator
used.
Why does the negative resistance of the oscillation circuit increase when the oscillator frequency is decreased?
Answer : The negative resistance of the oscillation circuit depends on the characteristics of the oscillation cell. When using the
circuit under the same circuit conditions, the negative resistance at a higher frequency decreases, because the gain of the
oscillation cell becomes lower at a higher frequency.
What is the maximum time value from when the clock doubler is turned "ON" to when the bus frequency is switched? (Target:
MB91F133)
Answer : The time from when DBLON[bit] of the gear control register (GCR) is set to when the DBLAK[bit] is switched cannot be determined.
Program so as to wait until the DBLAK[bit] is switched by loop or other processing.
