FAQ for FR Family

FLASH memory

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1. Which hardware sequence flag, DQ7 or DQ6, do we use for generating a program and erase programs?
2. When the Flash microcomputer operates with a lower voltage than the standard, does the read data of Flash become a fixed value (such as FFh fixed)?
3. Is "minimum 10,000 program/erase cycle guarantee" by Fujitsu based on "one count for program" and "one count for erase"? (Target: MB91F369)
4. How can we perform the function operation equivalent to Flash programming and erasing in "program mode" of SH-2?
5. Do the Flash program time and chip/sector erase time vary depending on the operating frequency of the microcomputer?
6. Are the standard values (maximum) of program time and sector erase time described on the datasheet the same as the standard time when the timing limit excess flag (DQ5) becomes 1?
7. Is there any order in which the addresses are to be erased, when sector erase or chip erase is executed for Flash?
8. When a Flash timing excess was detected by the timing limit excess flag DQ5 (DQ6 = "toggle" and DQ5 = "1"), does the RDYINT bit become "1"?
9. When we intend to set PLL to 33-MHz operation (16.5 MHz source oscillation, during using PLL), the operation becomes unstable immediately after the setup. (The address fetch is doubtful.) (Target: MB91150 series)
10. By the Fujitsu's PC programmer, ERASE terminates normally, but BLANK CHECK results in "NG". What can be considered?

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Which hardware sequence flag, DQ7 or DQ6, do we use for generating a program and erase programs?

• Answer :
  You can use either hardware sequence flag DQ7 or DQ6. The termination of program/erase is judged with DQ7 and DQ5 or DQ6 and DQ5.

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When the Flash microcomputer operates with a lower voltage than the standard, does the read data of Flash become a fixed value (such as FFh fixed)?

• Answer :
  It does not become a fixed value. The data read during an operation with a lower voltage than the standard is undefined.

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Is "minimum 10,000 program/erase cycle guarantee" by Fujitsu based on "one count for program" and "one count for erase"? (Target: MB91F369)

• Answer :
  Minimum 10,000 cycle guarantee means that 10,000 counts of "erase only" are guaranteed.

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How can we perform the function operation equivalent to Flash programming and erasing in "program mode" of SH-2?

• Answer :
  The BOOT program has the function for transferring the program received from UART to the specified address. Use the function to download the program to be programmed to the internal RAM for the execution.

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Do the Flash program time and chip/sector erase time vary depending on the operating frequency of the microcomputer?

• Answer :
  They do not depend on the operating frequency of the microcomputer.

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Are the standard values (maximum) of program time and sector erase time described on the datasheet the same as the standard time when the timing limit excess flag (DQ5) becomes 1?

• Answer :
  
  • Maximum value of program time: Time when the timing limit excess flag is set.
  • Maximum value of sector erase time: Not the time when the timing limit excess flag is set. It takes about one minute until the timing limit excess flag is set at sector erase.

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Is there any order in which the addresses are to be erased, when sector erase or chip erase is executed for Flash?

• Answer :
  There is no specific order in which the addresses are erased. Individual Flash cells are erased at the same time. Since the erase time varies for each Flash cell, cells will have been erased in the descending order of speed of the erase time characteristics.

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When a Flash timing excess was detected by the timing limit excess flag DQ5 (DQ6 = "toggle" and DQ5 = "1"), does the RDYINT bit become "1"?

• Answer :
  When a Flash timing excess is detected by the timing limit excess flag DQ5 (DQ6 = "toggle" and DQ5 = "1"), neither the RDYINT bit nor RDY bit becomes "1." Therefore, the Flash error status (timing limit excess) cannot be detected by the Flash memory control status register (FMCS). It can be detected only by the Flash hardware sequence flag.

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When we intend to set PLL to 33-MHz operation (16.5 MHz source oscillation, during using PLL), the operation becomes unstable immediately after the setup. (The address fetch is doubtful.) (Target: MB91150 series)

• Answer :
  Set the FACH bit of the FWTC register to the high-speed read mode.

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By the Fujitsu's PC programmer, ERASE terminates normally, but BLANK CHECK results in "NG". What can be considered?

• Answer :
  Does the program/erase power supply voltage become too lower than be guaranteed? With a lower voltage value not guaranteed, this status occurs.