Is the DMAACK signal output during the DMA transfer or when informing of the transfer acceptance? (Target: MB91101)
Answer : You can specify the timing when the transfer request acceptance output signal is generated by the AKSE and AKDE bits of the
DMAC pin control register. The time of data access at either the transfer source or transfer destination can be specified.
Is it possible to alternately execute DMA and MPU external bus accesses? Can we perform DMA and MPU accesses in parallel like
DMA transfer, MPU external bus access, DMA transfer, MPU external bus access, and so on? (Target: MB91360)
Answer : To control the flow of DMA transfer, MPU external bus access, DMA transfer, MPU external bus access, use the request signal
of DMA. (For details, see the description on the DREQ pin in the manual.
While transferring data from the external SRAM to internal RAM by DMA, when the A/D conversion is executed in parallel, the
conversion value can be an abnormal value (more than the overall errors). (Target: MB91FV360GA)
Answer : Set the operation mode of the A/D converter to the stop mode.
Is the parallel alternative execution of multiple DMA transfers possible? Can we execute different multiple DMA channels
alternately like DMA transfer: Ach (1 cycle), DMA transfer: Bch (1 cycle), DMA transfer: Ach (1 cycle), DMA transfer: Bch
(1 cycle), and so on? (Target: MB91360)
Answer : You can alternately activate two DMA transfers by using the rotational mode of DMA.
Is it possible to activate DMAC by using the interrupt of A/D converter and transfer the A/D conversion result to RAM? (Target:
MB91260A series)
Answer : MB91260A has three units of built-in A/D converters, which are designed to be activated at the same time to acquire the conversion
result. In this case, because the conversion result by the three units cannot be transferred by the DMAC transfer, the program
processing is assumed. Therefore, neither DMAC activation nor transfer by the A/D interrupt is supported.
Is the DMA transfer request accepted at "H"? (Target: MB91101)
Answer : You can specify the DREQ detection level by the LSn1 and LSn0 bits of the DMAC pin control register. The rising edge, falling
edge, H level, and L level can be specified.
